Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom?

In this review, we discuss the progress of emerging dry processes for nanoscale fabrication of high-aspect-ratio features, including emerging design technology for manufacturability. Experts in the fields of plasma processing have contributed to addressing the increasingly challenging demands of nanoscale deposition and etching technologies for high-aspect-ratio features. The discussion of our atomic-scale understanding of physicochemical reactions involving ion bombardment and neutral transport presents the major challenges shared across the plasma science and technology community. Focus is placed on advances in fabrication technology that control surface reactions on three-dimensional features, as well as state-of-the-art techniques used in semiconductor manufacturing with a brief summary of future challenges.


Introduction
Currently, feature miniaturization in semiconductor fabrication is continuing through newly proposed nanoscale and atomic layer control processes. 1) In 1959, Richard Feynman made the now famous statement that "there is plenty of room at the bottom", referring to the manipulation of matter on the atomic scale. 2) In the same year, the first integrated circuit (IC) comprising germanium mesa bipolar transistors was developed. 3) Shortly thereafter, the monolithic planar process was realized. 4) In the 58 years since then, semiconductor technology has made astonishing progress, leading to today's microprocessing units (MPUs) that comprise multiple billions of transistors with feature sizes quickly approaching atomic dimensions, 5) as well as dynamic random access memory (DRAM) with 50 trillion one-transistor=onecapacitor (1T1C) structures fabricated in a diameter of 300 mm wafer. 6) DRAM is a volatile memory, and the NOT-AND (NAND) type flash architecture using floating-gate transistors is an electronic nonvolatile memory. In 2008, an epoch-making three-dimensional (3D) gate stack NAND flash memory (3D-NAND) was developed to replace the planar two-dimensional (2D) flash memory. 7) Today, flash memory cells with an impressive 512 GB per die are achieved by forming a 64-layer gate stack. 8,9) The semiconductor memory market was expected to increase to close to $85 billion in 2017 and continue to grow to over $100 billion in 2020. 10) Manufacturers are continuing to shrink feature sizes and to scale vertically to increase the bit density and meet demand while maintaininga cost advantage over their competition. This is driving new challenges in dry etching processes to meet the demands of the ever-shrinking size and=or dramatically increasing aspect ratio of the features required for the next generation of chips. Fabrication of vertical gate stack structures requires HAR etching, resulting in dimension scaling from two to three dimensions (Fig. 1).
Developments in DRAM and 3D-NAND technologies have continued to scale through 3D integration and advanced pitch multiplication schemes. The capabilities of dry etching are continuing to downsize IC features from one generation to the next. The ability to make small features and control feature-size variation enables the fabrication of HAR features in high-volume manufacturing.
In complementary metal oxide semiconductor (CMOS) logic gates, since the advent of the production of fin field electric transistor (finFET) devices in 2011, device architectures have fundamentally adopted a 3D design. 11) Process technology for etched vertical profiles with high aspect ratios (HARs), clean gate sidewalls free of etching process residue, minimal erosion of liner oxide films protecting key architectural elements such as fins, and residue-free corners at gate interfaces with critical device elements requires the establishment of design technology co-optimization (DTCO) or design technology for manufacturing (DFM) in device architectures and CMOS layout design for the perturbationfree process variations (Fig. 1). 11) First, we introduce the history of feature scaling, involving the transition from lithography scaling to film=etching-based multiple-patterning scaling, leading to the scaling from two to three dimensions. The critical dimension (CD), that is, the smallest geometrical feature, will be reduced in two dimensions by the introduction of higher-resolution lithographic tools with an extreme ultraviolet (EUV) light source, directed-self-assembly (DSA) materials, and other techniques. Second, we review the background and science of HAR etching technology, especially to give an atomic scale understanding of surface reactions at hole bottoms. The transport of charged particles (electrons; positive and negative ions) and neutral particles ("neutrals") is reviewed to clarify the actual surface reactions. Third, macroscopic wafer-scale CD uniformity is examined to realize highvolume manufacturing. Traditionally, microloading effects, reactive ion etching (RIE) lag, and aspect-ratio-dependent etching (ARDE) have been studied. Under the HAR requirement, etched profile distortions become a significant issue for CD control at the bottom of features such as holes. Fourth, focus is placed on emerging processing technology and DFM. To control the CDs at the bottom of deep features, self-limiting reactions have attracted much attention.
Here we review nanoscale and atomic layer processing while focusing on the following topics: (1) advances in the development of atomic layer processing for HAR features achieving 2D to 3D scaling, (2) future challenges to controlling CDs, (3) CD uniformity at the feature and wafer scales, and (4) CDs at the bottom of deep features. The fin-FET is one of the leading 3D devices, but its fabrication faces the problems of uniformity in film deposition and material etching. In particular, using atomic layer deposition (ALD) and atomic layer etching (ALEt) as boosting technologies, we discuss how the self-limiting surface reaction achieves CD control. Furthermore, we present an overview of possible technology ideas that can enable a continued increase in the number of functions per unit cost for the next two decades. The topic of DFM will be reviewed. One purpose of scaling is to realize new device features with low power consumption and high performance in terms of power, performance, area, cost, reliability, and manufacturability (PPACR). Accordingly, we should continue to explore new methods that provide solutions. The coordination of developments among technology, design, and systems, such as design technology system co-optimization (DTSCO), DTCO, and system and technology co-optimization (STCO), will enable us to overcome scaling hurdles more easily than by traditional methods. We also discuss new approaches to feature miniaturization.

Background on film/etching-based multiplepatterning scaling
The pattern density of memory devices has been dramatically increasing for decades. To integrate high-density circuits in a small chip, it was necessary to decrease feature sizes and increase the aspect ratios of interconnecting structures. Memory technologies are continuing to scale in dimensions. A 300-mm wafer now contains close to 400 die and 50 trillion features. 6) In the past, the photolithographic CDs determined the feature dimensions. Since 2017, film and etching multiplication technology has provided planar features with CDs smaller than the photolithographic resolution. DRAM is still scaling in two dimensions and the memory industry has adopted various pitch multiplication schemes to overcome the limitations of standard lithography.
Methods for producing sub-resolution mask patterns are roughly classified into (1) double exposure, (2) double patterning or the litho-etch-litho-etch (LELE) process, and (3) self-aligned spacer double patterning (Fig. 2). The main technique has become the spacer (sidewall) image transfer (SIT), as developed in 1984. 12) The SIT process scheme is as follows. First, dummy mask patterns, for instance, developed resist-patterned masks, are coated by conformal films, such as oxide films. Then, the oxide films are etched off by anisotropic directional etching until the underlying substrate is exposed. The dummy masks leave surrounding collars of the oxides. The dummy masks are then removed so that only the collar features remain. Thus, the collar widths are controlled by the verticality of the sidewalls of the dummy mask and the conformality of the sidewall films. The pattern density can be doubled by the SIT method. [13][14][15][16] The SIT patterning process is well adapted to state-of-the-art nanoelectronics developments. [17][18][19][20][21] Furthermore, the double patterning can be conducted twice to achieve quadruple patterning. 22) Current lithography technology has enabled the patterning of high-density sub-15-nm features for DRAM. 23) Although the SIT method achieves smaller CDs, its drawback is the process complexity of the film=etchingbased multiple patterning. To reduce the process complexity and cost, the adoption of EUV in memory manufacturing lithography, motivated by cost reduction in high-volume manufacturing, has been postponed until around 2021 (Fig. 3). 24) Because the SIT process was adopted with a finer photolithographic pattern, the original EUV pattern dimensions will reduce the complexity of quadruple-and multiple-patterning processes. EUV photolithography is described elsewhere. 25,26) As discussed above, traditional scaling was driven by lithographic improvements to reduce the CD. In this first generation, photolithographic scaling was successful and improved device performances. Over the last decade, a second generation of multiple-patterning methods, such as the SIT process, has provided alternative ways of subresolution patterning for photolithography. In the next decade, EUV with double patterning will play a role and eventually replace the current multiple-patterning methods. In addition, the transition from two dimensions to three dimensions is continuing to decrease device scales, in combination with dry processes involving film deposition and material etching.
When EUV high-resolution patterning is achieved to meet HAR profile control, the limiting factors for downsizing future DRAM nodes will be the variations in the pitch multiplication process (Table I). Physical parameter variations such as CD result to electrical parameter variations such as capacitance, current conductance, and leakage. Thus, the manufacturing processes are affected the variations to the device performances such as power consumption, delay, and reliability. To determine correlations in the physical parameters with electrical parameters are made with modeling and it is used statistical process control. Most commonly, the variations are distributed with Gaussian distributions. As noted, the statistics are categorized in systematic and nonsystematic components. Even if the physical device parameters are normally distributed, the dependence of the electrical device parameters on these physical parameters may not be linear, giving rise to non-Gaussian. 27) Even in 2D scaling, CD uniformity is a key issue for 300 mm wafer production lines. The CD uniformity should be controlled at both the feature and wafer scales, where these variations are known as microloading effects and loading effects, respectively.

2D CD control
3.1 Wafer-scale control of planar CD uniformity Block copolymers have received much attention as an approach to solving the CD uniformity problem. Bates et al. reported a thermodynamic mechanism for controlling the structure of block copolymerization. 28 30) Thereafter, Bencher et al. reported their trials for sub-lithographic patterning using a block copolymer mask. 31) Servin et al. introduced a directed self-assembly (DSA) process to increase CD uniformity due to diblock copolymerization with a natural period. 32) The nature of self-assembly is useful for the realization of a tremendously narrow CD distribution.
3.2 HAR feature profile control: From two dimensions to three dimensions In the late 1990s, reactive ion etching (RIE) equipment, such as inductively coupled plasma (ICP) and electron cyclotron resonance (ECR) equiptment, was introduced to provide a high-density plasma source. Soon afterward, charge build-up at the bottom of HAR mask patterns became an issue. This phenomenon is caused by the electron shading effect, 33) and it occurs when the charge neutralization at the bottom is unbalanced. In addition, this shading effect governs the charging damage of transistors, by conducting current from the plasma into the dielectrics. 34) Vertical isotropy of etched features is obtained by ion transport during plasma sheath formation. In principle, positive and negative particles should have the same trajectories inside a hole and equalize the charge at the HAR hole bottom. Alternatively, if negative ions can move inside an HAR hole and reach the bottom in the same way as positive ions, the charges will be well balanced and solve the charge build-up issue. However, efforts are continuing to achieve this balance.
In pulsed plasma excitation, during "off periods", electronegative molecules receive abundantly electrons to generate negative ions. As a result, the volume fills with positive and negative ions. This means that sheaths in front of the surface collapse and reduce the plasma potential. This behavior helps to solve the charge neutralization problem inside features. Pulse plasma technologies are reviewed elsewhere. 35,36) The transport of ions and neutrals inside HAR features is becoming important, and transport can be modified by  Table I. Sources of variation in pitch multiplication process.
1. Feature-to-feature CD variation or local CD line variation (LCV) 2. Field-to-field within wafer CD (WIW) variation or across chip line variation (ACLV) 3. Wafer-to-wafer CD (WTW) variation or across wafer line variation (AWLV) reflection and adsorption of the species on the sidewalls of HAR features. Recently, the control settings of plasma equipment to achieve optimal charge transport have been debated, with some arguing for the synchronous application of bias power or a direct current (dc) bias. [37][38][39] For instance, Tokashiki et al. reported that the adoption of synchronous pulse plasma etching technology improved the CD uniformity for large-diameter wafers owing to control of the ion flux and energy as well as radical-to-ion flux ratios. 40) In addition to charged particle transport, the wafer temperature plays an important role in the control of etched feature profiles and CD uniformity. Kanno et al. pointed out that the adsorption of etchants and inhibitors is influenced by temperature, and that a gate CD could be controlled by controlling the wafer temperature. 41 reported that dissociation of large-mass fluorocarbon molecules was suppressed by low-pressure pulsed plasma, leading to high-selectivity etching due to control of polymer deposition. [45][46][47] For the purpose of increasing wafer-to-wafer CD uniformity, the model prediction method was used to resolve the process drift or shift of CD uniformity. 48) To date, various advanced process control (APC) approaches have been used to achieve CD uniformity in high-volume manufacturing.
Thus, uniformity within features and across a wafer has reportedly been controlled with respect to ions, neutrals, and reaction surface temperatures. In addition to surface reactions at the HAR bottom, fluxes and energies of charged particles, that is, electrons and positively and negatively charged ions, should be balanced to create a more neutral reaction environment. For ideal RIE, neutrals such as reactive radicals, "absorbates", play an important role in the synergism of the adsorbate surface under ion irradiation. Excessive deposition may distort the etched profile owing to by-products and redeposition, that is, "evacuation or exhaustion", which is becoming more important for CD control (Fig. 4).
Presently, 3D scaling plays a key role in increasing device density. Nevertheless, the 2D downsizing of DRAM cells also increases the DRAM capacitor aspect ratio. At the same time, more stringent requirements for profile control and CD uniformity must be addressed. Here, focus is placed on (1) distortion of the etched profile and (2) CD uniformity at the HAR bottom. Etching rates have become so low that they are no longer economically viable. It is necessary to develop high-etching-rate methods without distortion of the etched profile. Overall, macroscopic etching rates depend on the aspect ratio and pattern, that is, the ARDE phenomenon. To compensate for ARDE, equipment development has focused on increasing the radio-frequency (RF) bias power and flow conductance.
Enomoto et al. reported profile distortion in SiO 2 etching with CF 4 plasma in 1979. 94) Oehrlein and Kurogi reviewed the SiO 2 sidewall chemistry in 1998. 95) Ikegami et al. reported that bowing at the sidewalls occurred by reducing the ion flux and energy in HAR holes and by the bending of trajectories of the incident ions at mask edges. 96) Izawa et al. found that radical transport inside HAR features affected the adhesion of etching protection films at the sidewalls due to less protection against ion-sputtering erosion. 97) Miyake et al. pointed out that taper angle masks scattered incident ions, causing the bowing of sidewalls in HAR holes. 98) Similar ion scattering at sidewall surfaces caused necking and bowing of the feature profiles, as found by the Moon group. 82,83) Kamibayashi et al. discussed the effect of wafer bias frequencies on etched profiles. 99) Negishi and co-workers reported that the mask edge roughness was transferred with amplification of the roughness amplitude, leading to deformed pattern profiles with profile distortion at the hole bottom. 100,101) Such profile distortion problems have always been an issue for the plasma-etching fabrication of HAR features.
The historical trend of HAR contact hole (HARC) etching has been to develop equipment with higher bias power and larger flow conductance to etch deeper holes. As the aspect ratio of the hole increases, the etching rate dramatically decreases because the flux of ions and neutrals is too limited to reach the etching front. 102) To conduct the highly selective etching required for SiO 2 over a thin masking photoresist film and the underlying films such as the Si substrate, W film, and Si 3 N 4 film, dominant etching of SiO 2 is achieved by supplying radicals such as CF x species, and the reaction needs a relatively high energy induced by ion irradiation. 102) This synergistic reactions of radicals and ions also requires sufficient amounts of reactive etchants (radicals and ions). [103][104][105][106] Tatsumi et al. reported that etching rates under irradiation of highly energetic ions were determined by a number of F atoms in a few nanometer of a SiO 2 film to a covered polymeric layer which was formed by radical adsorption. 107) This means that ion energy in sheath and adsorbed polymer layer thickness on the surface are correlated with etching rates, as a summary of several researches. [108][109][110][111][112][113][114][115][116][117][118] In this situation, the wafer temperature has been the key cause of anomalous etched profiles with, for example, bowing and necking. At low wafer temperatures, excessive deposition occurs at the entrance of HAR holes and insufficient deposition occurs at the hole bottom. In contrast, at high wafer temperatures, the reduced sticking of CF x radicals increases the transport of radicals into deeper parts of the hole. 119) The problem of absolute radical fluxes inside HAR holes has not been completely solved yet. Accordingly, HAR feature dimension control extends to the 3D-CD at the HAR bottom.

Radical transport and ion transport inside HAR features
The etching process for HARCs became a key process for memory devices, as described in Fig. 4. As memory technology moved on from laterally shrinking devices to vertically stacked devices, 3D-NAND was scaled up by adding more vertically integrated tiers of the oxide-polyoxide-poly (OPOP) or oxide-nitride-oxide-nitride (ONON) films that are used to fabricate NAND memory cells. 120) Therefore, the process capability for pillar etching is the limiting factor for increasing the bit density and reducing the per-bit node cost. As pillars are vertically scaled and the aspect ratio increases, the demands on the hard-mask technology and profile control increase and require the development of new processing technologies to maintain the CDs of the NAND memory cell throughout the pillar height.
Ion energy control by increasing the effective bias power for HAR features continues to advance. Great effort was made to increase ion energies to overcome charge build-up on the etching front inside HAR holes. Based on the trend of bias power in the past few years, the required power this year will exceed 25 kW, as shown in Fig. 5. 121) The ion energy distribution function (IED) depends on the frequency of RF excitation power with the bias power remains the same. For simplification, the ion energies are considered here on the basis of the effective bias power required to produce the same ion energy at a frequency of 2 MHz, regardless of the actual RF excitation power. To control the ion energy at an HAR hole bottom, higher bias power is becoming a critical technology for dielectric etchers. 121) A new boosting technology is needed.
Many challenges arise when the bias power is increased. The prevention of arcing and effective cooling, and power delivery systems are all critical for enabling high-power capability. Moreover, it is harder to compensate for neutral fluxes with increasing aspect ratio, because the neutral species are transferred only by diffusion through the holes.
Pulse bias technology, which simply ramps up the bias power, was introduced almost 10 years ago. 36,[122][123][124] In the off period of the pulse operation, the sheath collapses and the potential at the wafer surface decreases, which allows electrons and negative ions to reach the etching front, thus neutralizing the positive charge build-up. This charge neutralization helps to increase the effective bias power and suppresses the accumulation of positive charges at the hole bottom owing to the transport of negative ions during the pulse-off phase. The IED and ion angular distribution (IAD) are affected by the charge exchange collision within the plasma sheath. In the late 1990s, a mass-selected ion energy analyzer for RF electrodes was developed by Mizutani and Hayashi,[125][126][127] and a bias frequency dependence of the actual IED was reported by Hikosaka et al. 128) In 2000, Noda et al. reported on ion transport in HAR holes with a diameter of 200 nm in SiO 2 etching with a fluorocarbon plasma. 129) The results showed that the ion flux and the ion energy were depressed at the bottom surface and strongly depended on the hole aspect ratio. 129) Recently, a low-frequency bias power, especially 400 kHz, has been used with HARC etchers. Typical process plasmas have an electron density on the order of 10 11 cm −3 . 130) By applying bias power to develop high-voltage sheaths, sheath widths increase to a range on the order of millimeters. 130) As a result, the transit time of accelerating ion in the sheath is close to the half-period for a frequency of 400 kHz. Namely, since the ion travels with this half-period, the peak ion energy is maximized. When the same RF power is applied, the lower bias frequency of 400 kHz produces higher ion energies. Thus, a bias frequency of 400 kHz instead of the usual 2 MHz was implemented when applying the bias power. For low bias frequencies, ions transiting through the sheath in a small fraction of an RF period arrive with energy dependent on the phase and voltage of the bias when the ion enters the sheath. 131) For high bias frequencies, ions transiting through the sheath over many RF periods arrive at the substrate with a narrower distribution centered about the average sheath potential. 131) This motivated the use of multiple bias frequencies to customize the IEDs using a chirp, whose frequency was varied over time with an arbitrary waveform. 131) Lamham and Kushner reported the computational results for biasing substrates using chirped frequencies in high-density, electronegative ICPs. 131) The IED depended on the frequency range and chirp duration owing to transient shifts in the self-generated dc bias. 131) In addition, ions are transported from the plasma through the sheath to the surface. The IAD is actually spread over 5-10°around the essentially normal incidence angle. To investigate obliquely incident ions, Ui et al. reported that a bimodal IAD that consisted of ions obliquely incident mainly from two directions was controlled by modulation of RF power applied to four cathodes grouped with a phase shift. A nearly uniform IAD was obtained across the wafer. 132) The anisotropic ions scatter at the mask edges and form specular reflections at the sidewalls of the mask and inside HAR features. However, no actual divergence of the IAD was measured.
To allow transport into deeper holes, advances in equipment have traditionally focused on increasing flow conductance and bias power. To achieve this, a new technology or approach is required for further advances.
This HAR etching trend is no longer viable as ARDE poses some critical limitations that cannot be overcome with the same approach. The transport of radicals and ions is the key issue in HARC etching. To enhance flux to the etching front, flow conductance was increased to maintain the purity of the bulk plasma with respect to the etching by-products. This increases the diffusion of new reactants into holes and removes by-products faster. Another way to enhance flux is to increase the temperature.

Cyclic and cryogenic processes for HAR patterning
In 1986, time-modulated (cyclic) etching was reported by Tsujimoto and Tachi. 133,134) In 1988, cryogenic etching conducted at temperatures below 0°C was proposed by Tsujimoto et al. 135) To reduce the sidewall etching by both spontaneous radical reactions and ion-assisted reactions, a cyclic and cryogenic process was developed. Gotoh et al. reported that the estimation of IADs by fitting a crosssectional profile to the simulated profile as parameterized by IADs versus the normalized etched depth. 136) Under conditions of low pressure and high dissociations of both reaction byproducts and feedstock gases with a long residence time and high-density plasma, the mechanism of redeposition becomes complex. Tsujimoto et al. reported a high-flow etching apparatus that was equipped with a high-speed pumping system. 134) They concluded that a cyclic and cryogenic process (with low pressure, high gas flow, and low temperature) was necessary, especially for n + -doped silicon anisotropic etching, due to thin sidewall protection. 134) Kamto et al. reported the formation of through-silicon vias by ICP etching using SF 6 =O 2 gas chemistry at cryogenic temperatures. 137) Control of the taper shape is critical in the optimization of the parameters for the gas flow rate, chamber pressure, ICP power, and substrate temperature. 137) Therefore, chemical reactions with regard to both sidewall protection and ion-assisted reactions were indispensable for the realization of HAR features with high-volume manufacturability.
Recently, Parasuraman et al. reported successful patterning with an aspect ratio of 160 using a cyclic and cryogenic etching process for micro-electro-mechanical systems (MEMS) fabrication (Fig. 6). 138) Conventionally, a fluorocarbon layer is used as a passivation layer to etch silicon  (Color online) Aspect ratio versus feature size as studied by various groups for feature sizes ranging from 10 nm to 10 µm order, as originally plotted by Parasuraman et al. 138) oxide selectively. Accordingly, to etch through this passivation layer, the ion energy must be high enough to penetrate the layer. Giving ions directionality by supplying RF power allows us to etch anisotropically. However, when the thermal energy of the substrate is very low (lower than the reaction threshold energy), etching does not happen spontaneously even without a passivation layer. In this situation, a very low ion energy is required to etch anisotropically. Based on this concept, etching at cryogenic temperatures was introduced to MEMS fabrication. In addition to the cyclic process, a decrease in the treatment temperature enabled successful patterning etching at −110°C with an aspect ratio of 125 as reported by Parasuraman et al. 138) Unfortunately these technologies are far from ready for mass production in the semiconductor industry, even though they have already been introduced for MEMS devices. (Fig. 6) Solid lines represent the trend when only the width is reduced while the depth is maintained.
As shown in Fig. 6, Parasuraman et al. obtained empirical ARDE data that followed a semi-logarithmic law when a narrow feature width has a shallower depth. 138) By extrapolating the trend of vanishing width, the ultimate aspect ratio for specific etching techniques were evaluated and the predictive ratio would maximize at around 3,000 because of processes free from aspect ratio dependence. 138) Since a minimum thickness for the passivation layer is not included in the vanishing width, the experimental results prone to less than the predictive ratio.

Wet processes for HAR patterning
The wet process of metal-assisted catalyzed etching (MaCE) successfully fabricated HAR features in Si with an aspect ratio greater than 100. This process involves depositing a metal catalyst onto a Si substrate and immersing it in a bath containing hydrofluoric acid and an oxidizer such as hydrogen peroxide. The Si is only etched where the catalyzed metal contacts the surface by local oxidation of Si and etching of the oxide by etchants. The directional etching of Si is obtained by oxidation of the Si that is underneath the gold to an ionic form and the reduction of oxidants (H 2 O 2 ), catalyzed by the gold, which produces holes (h + ) in the Si. The product (H 2 SiF 6 ) is soluble in HF. This process results in the removal of Si without any consumption of Au. The overall reaction for MaCE of Si with H 2 O 2 and HF in a water solution catalyzed by Au can be written as where H 2 O 2 + 2H+ → 2H 2 O + h + is the reaction at the cathode (reduction) side and Si + 6HF + 2h + → H 2 SiF 6 + H 2 + h + is the reaction at the anode (oxidation) side (Fig. 7). This implies that the etching direction is affected by the electron-hole concentration gradient in the charge carrier diffusion direction. 139) Electric bias attenuates the etching in MaCE. 140) As noted, the electrochemical etching reactions of Si are well known and the phenomenon was originally discovered in porous silicon formation by Uhlir in the 1950s. 141,142) Si nanowire (NW) arrays were also fabricated by MaCE. [143][144][145][146] Features in GaAs were successfully fabricated using potassium permanganate and sulfuric acid etchant solutions. 147) For an InP substrate, hydrogen peroxide and sulfuric acid are used. 148) In 2005, Tsujino and Matsumura applied MaCE to form a cylindrical hole in Si with a diameter of 50 nm and a depth of more than 40 µm. 149 152) To realize MaCE in high-volume manufacturing, the patterning with metal catalysts, the removal of the catalysts, and the removal of contaminants must at least be considered. As a reference, MaCE may inspire the utilization of etching with controlled vertical directionality.
In this section, we reviewed processes for fabricating HAR features and controlling their CD uniformity. While the ALEt process has already been introduced, it still suffers from the aforementioned disadvantages. It is evident that conventional HARC technology will not be sufficient in the near future. A new approach will soon be needed to etch holes with aspect ratios greater than 100.

Boosting technologies for CD control at bottom of HAR features
4.1 Self-limiting reactions to improve CD uniformity Scaling from two to three dimensions and CD uniformity might be achieved by incorporating self-limiting reactions into fabrication processes. This emerging technology is required for the formation of contact holes with aspect ratios greater than 100, which remains harder than ever to achieve. It is evident that new approaches are required to continue the rate of advancement of previous years.
ALEt is a very challenging process, which offers improvements in selectivity and etching profiles but suffers from a  loss of throughput. Since the idea was suggested, many researchers have tried to improve both the throughput and etching profiles simultaneously. In recent years, the ALEt process has developed dramatically but not to the same degree as ALD which was successfully introduced into production on the deposition side.

ALD of SiO 2 , Si 3 N 4 , and SiC
The current state-of-the-art precursors, plasmas, and process conditions required to deposit conformal silicon dielectrics by plasma ALD are discussed here. Theoretical and experimental data will explain the observed reaction characteristics for the plasma ALD of SiO 2 and Si 3 N 4 , and the lack of success (so far) for SiC. Although plasma enables low-temperature deposition, it poses challenges in achieving isotropic film properties over the complex topography of today's semiconductor devices.  4 ], and tetrakis(diethylamido)hafnium [Hf(NEt 2 ) 4 ]and water for oxidation. 154) They pointed out that the alkylamide metal precursors were able to deposit smooth and conformal metal oxide films at temperatures as low as 50°C. 154) In contrast, diketonate and alkoxide precursors require a relatively high deposition temperature for precursor decomposition; however, the films were roughened by crystallization. 154) Chloride and iodide precursors can be decomposed at temperatures as low as 180°C; however, halogen impurities are incorporated into the films, and this cannot be prevented at low temperatures. 154) Etching of the growing surface by the precursors themselves causes additional surface roughening and nonconformity. 154) As the dimensions of modern semiconductor devices continue to shrink below the current 14-nm technology node, novel processes for the deposition of highly conformal, low temperature, and silicon-based dielectrics will be needed for applications that include sidewall spacers, barriers, and pattern layers. ALD is an ideal method for achieving high conformality and has been used in high volume manufacturing to deposit high-k dielectric materials (e.g., HfO 2 and ZrO 2 ) for several technology generations.
Plasma-assisted ALD is the best-known method to meet low temperature (<500°C) requirements, and it is currently used for depositing conformal silicon dielectrics such as SiO 2 and Si 3 N 4 . [155][156][157][158] Typical dielectric ALD processing involves two discrete precursor steps: the first for the metal=silicon atoms and the second for the co-reactant (C, N, or O). These sequences are examined here in the context of the reaction mechanisms occurring during each step (Fig. 8). Silicon precursor selection is a daunting task, as nearly 10,000 silicon compounds are commercially available. 159) These can be broadly grouped into six categories: amides, halides, alkoxides, hydrides, and alkyls (Table II). Predictions have been made that each ligand on a surface becomes replaced through reactions. 160,161) When applying plasmas for silicon dielectric ALD, the other half-reaction in each ALD processing step typically involves oxidation, nitridation, or carbonization to form silicon oxide, silicon nitride, or silicon carbide, respectively. To simultaneously achieve good film properties at a low temperature, plasmas are required for the co-reactant step. [154][155][156] Ovanesyan and co-workers reported a SiN x process employing a Si 2 Cl 6 and NH 3 plasma at 400°C 154) as well as SiCN x processes employing a Si 2 Cl 6 and CH 3 NH 2 plasma at 400°C 155) and a SiCl 2 (CH 3 ) 2 and NH 3 plasma at 350°C. 161 164) Surface reactions during the ALD cycle were observed in situ by attenuated total reflection Fourier transform infrared spectroscopy (ATR-FTIR) with a ZnSe internal reflection prism. 154,155,158,[165][166][167][168][169][170][171][172] This technique enabled the in situ characterization of noninvasively probe-hindered intermediate species formed during the reactions. Surface -NH 2 and -NH species can be detected during Si-N-Si bond formation.
These precursors and N 2 plasma were used to apply deposits on HAR features, and the resulting growth per cycle (GPC) at the bottom was lower than that at the top. 156) This implied that charge-free N radical species are isotropic or nondirectional in nature, which means that they can collide   and recombine at the vertical surfaces of the trench nanostructures before they reach the bottom of the trench. 156) Challenges arise in achieving high conformality at the HAR bottom with different chemical sources and plasma processes. Despite isotropic deposition on both sidewalls and horizontal surfaces, the anisotropic nature of ion bombardment preferentially improves film properties. 156) Thus, a trade-off relationship between high conformality and high quality is observed for film deposition on 3D topographies. 156) In addition, the surface roughness increases as the number of processing cycles increases. The rounded corners of deposited film and small amounts of impurities in the film composed of elements of the processing gases were studied experimentally and computationally in ALD deposition of SiN film using hexachlorodisilane and hydrazine. 173) They speculated that plasma could generate undercoordinated surface sites such as nitrogen dangling bonds, and subsequent precursor adsorption occurred non-uniform surface covered with both -Si-H and silyl (-SiH 3 ) groups. The resultant -Si-H surface may rapidly react, as compared with the -SiH 3 site. This rate-difference causes to remain unreacted bonds and to give rise non-conformality. In addition, during plasma step, the fragmented ligand species could be redeposited as impurities on the growing film surface. 157) To solve the problems of conformality and quality, stringent control of ion and radical transport inside HAR features by controlling the plasma sheath is challenging.

Self-limiting surface reactions for atomic-level control in Al 2 O 3 ALD
The factors that lead to self-limiting surface reactions are outlined here. The defining characteristic of ALD is reviewed using experimental data from the literature. Ligands can persist at low temperatures, as explained via computed activation energies that show the so-called cooperative effect. A reaction mechanism for oxygen plasma was also computed. One of the attractive features of ALD is that it works at much lower temperatures (e.g., 150-300°C) than comparable chemical vapor deposition processes, and this enables deposition onto thermally sensitive substrates. In some cases, ALD can be achieved at even lower temperatures, but such temperatures often require plasma, as the thermal process may have a too low growth rate to be useful. The prototypical ALD process of TMA and water is one such example. In this process, the amount of alumina deposited in an ALD cycle drops steadily as the growth temperature is reduced below 200°C, whereas the growth rate is maintained even down to room temperature if TMA+O 2 plasma is used. It has long been supposed that the reason for this lies in thermal activation being required for some reaction step within the overall ALD process. Recent experiments and calculations have revealed which reaction step is involved, and this has modified our view of ALD surface chemistry. Experimental results from the Eindhoven University of Technology detected persistent methyl groups at the end of the H 2 O pulse in low-temperature alumina ALD, 174) and Stanford University obtained analogous results for zinc and tin oxide ALD. 175) Now, we present an overview of computed reaction mechanisms for thermal ALD. Specific surface reactions were previously computed to show coverage-dependent kinetics for alumina and hafnia ALD and to identify the types of species that can consequently be expected to persist at the surface. 176) Computed activation energies at metal oxide surfaces in different local environments show the central role played by the coordination number. Reaction from the anchor OH group to threefold coordinated Al(CH 3 ) 3 was in computation estimated an activation energy of 0.28 eV. Reaction from the other neighboring O to one-or two-coordinated Al(CH 3 ) x was higher activation energy of 0.74 eV, where the Al-C bond breaks by the proton transfer to the methyl group. 176) By computing complex surface models, the co-adsorption of precursors leads to a lower activation energy than previously reported. In some cases, these are the first reaction pathways computed to be viable at process temperatures. Undercoordinated oxygen is reactive towards the adsorption of Lewis acidic metal precursors, such as Al(CH 3 ) 3 and Hf(N(CH 3 ) 2 ) 4 , which in turn through the cooperative effect make hydroxyl groups more Brønsted acidic. A complementary set of reactions is observed when a ligand-covered surface is exposed to H 2 O, with co-adsorption activating both H 2 O towards dissociation and ligands towards protonation and desorption. These findings show how saturation of the coordination number can explain the selflimiting nature of ALD, from which the unique advantages of this technique are derived. These effects may be even more acute in the case of the thermal ALD of nitrides with the less reactive co-reagent NH 3 .
Comparison between the oxygen plasma and thermal H 2 O mechanisms shows a different mechanism for TMA+O 2plasma from that predicted by density functional theory. A range of gas-phase oxidation by-products are predicted by the calculations, with CH 2 O predominating. The prediction confirms that each ligand on the surface becomes replaced through oxidation by a hydroxyl group, independent of the by-product. 177) The factors leading to the densification of newly deposited Al atoms into bulklike coordinated structures are discussed, along with the consequences for the morphology of the film. Although the oxidation reactions of the plasma are initially spontaneous, they rapidly become self-limiting because of the limited reducing ability of the methyl-covered surface during ALD.

State-of-the-art of ALEt
Owing to the advantage of self-limiting surface reactions to achieve etching uniformity, ALEt has received much attention because it provides atomic-level control and material selectivity. The ALEt technologies are classified into anisotropic and isotropic etching (Fig. 9). The former classification includes digital etching, which is conducted in separate steps for etchant adsorption and removal of the generated volatile products after chemical reactions. 178,179) Anisotropic Cyclic process of ion-assisted reaction The anisotropic nature is obtained by vertical ion incidence to enhanced ion-assisted chemical reactions. Thus, this includes cyclical processes, which involve sidewall protection and ion-assisted reactions. Recently, the IED has been reconsidered for the optimization of ion-assisted reactions. A very narrow IED is provided by a beam etching system, in which ions are extracted by grid-type single or multiple electrodes. The use of RF bias control for ion-energy control gives a relatively broad IED or multiple peaks in the IED. Penetration depths of ions into the bombarded materials are determined statistically for their incidence energy; thus, a narrow IED band is desirable for controlling reactions at the atomic level. Comprehensive reviews are found elsewhere. [180][181][182][183] Tabata  Ar irradiation that improved material selectivity of SiN over Si. 186) In addition, the directional ALEt of GaN and AlGaN using cyclic Cl 2 plasma chemisorption and Ar ion removal was reported under conditions of low ion energy ranging from 50 to 100 eV within the self-limiting regime, as reported by Ohba et al. 187) In contrast, isotropic etching includes a sequential process for ammonium-salt-based modified layer formation and thermal evaporation of the salt, as originally reported for SiO 2 removal by Nishino et al. 188) The salt is essentially formed by a self-limiting reaction and remains on the reacted surface. Then, it is desorbed by thermal heating without leaving any residue on the surface. The isotropic and selflimiting properties are useful for conformality control in HAR features. Recently, Shinoda et al. reported the thermal cyclic etching of SiN, TiN, and W films developed on the basis of salt formation and thermal evaporation. [189][190][191][192] Kofuji et al. reported that a lateral sidewall of W was etched uniformly using NF 3 plasma chemistry. 193) In other words, the adsorption of reactants represents the processes of physisorption and chemisorption on the surface, and then complex salts form to bind the reactant as ligands with atoms that exist on the surface. If the complex formation is selflimiting and material-selective, and the product is volatile, then isotropic ALEt is enabled. A very important merit of plasma processing is that it enables the deposition and etching of materials with high quality at low temperatures through the use of energetic species present within the discharge, especially from an industrial perspective. 1) Plasma-enhanced ALEt at low temperatures has enabled selfaligned patterning, widely considered a breakthrough technology for improving CD uniformity and the downsizing of devices. Honda et al. extensively addressed self-limiting processes, such as ALEt, which adopted the advantage of the independence of the pattern density and the location on the wafer. 194) Namely, the atomic layer processes ALD and ALEt are free from aspect-ratio dependence due to their selflimiting nature. This property is indispensable for highvolume manufacturing.
5. Co-optimization among design, system, process, and technology for manufacturability

Basics of logic circuit design for fin-FETs
Currently, ultralarge scale integrated circuits (ULSIs) use a discrete CMOS transistor as a circuit element, which consumes less power than its bipolar counterparts. 195) The CMOS logic involves combinational circuits, whose outputs depend only on the current inputs, and sequential circuits, whose outputs depend on both current inputs and previous input, with registers as memory. 195) The physical implementation of the logic gates and the registers from transistors has a major impact on performance, power, and cost. 195) Previously, Mead and Conway popularized scalable design rules based on a single parameter λ that characterizes the resolution of the process. 195,196) Thereafter, a physical layout can be automatically generated that has a simple layout style based on a "line of diffusion" rule commonly used for standard cells in automated layout systems. 195) Note that this style consists of four horizontal strips: metal ground at the bottom of the cell, strips for n-diffusion and p-diffusion, and a metal power supply at the top. The power and ground lines are often called supply rails. 195) In contemporary standard cells, polysilicon is generally not used as a routing layer, so the cell must allow second-metal-layer to first-metal-layer (metal2-to-metal1) and first metal layer to polysilicon (metal1-to-poly) contacts for each gate. While this increases the size of the cell, it allows free access to all terminals in the metal routing (Mx) layers. 195) In the standard cell design flow, the logic design is created by a synthesis tool at the register transfer language (RTL) level. The synthesis tool maps the algorithmic description of the design into a collection of standardized Boolean logic functions expressed as NAND and NOR gates, inverters, latches, and other elements. Then the physical layout is rendered by an electronic design automation (EDA) tool and a standard cell library to build the appropriate place and route (PnR) solution. 197) The transistor structure moves from a planar to fin-FET structure with processes such as multiple patterning, self-aligned double patterning (SADP), and LELE and cuts. For this, the fin-FET layout design is also modified.
A major difference in the fin-FET design is the use of triple-gate (tri-gate) and double-gate structures. 198) In a shortgate (SG) structure, the left and right sides are connected together, but in an independent-gate (IG) structure, the top part of the wrap-around gate structure is etched out. 198) The fin-FET performance is affected by the cross-sectional area of the fin and the fin shape. 198) A triangular fin can reduce leakage current. 198,199) A rectangular fin has better short channel effect metrics, in particular, a sub-threshold slope, gate-induced-drain leakage (GIDL), and drain-induced barrier lowering (DIBL). These are caused by strengthening the electrostatic field without the coupling of field lines due to the small dimensions. Thus, increasing the fin heights directly improves performance, such as current drivability, and fin height has replaced width as the conventional design parameter.
Standard cells are defined by dimensions such as gate pitch (GP), contacted poly pitch (CPP), metal pitch (MP), cell height, and fin pitch (FP), as shown in Fig. 10. 200) The MP describes the smallest width and space combination allowed for the lowest metallization levels and primarily determines the cell height. 197) The CPP describes the tightest transistor placement and primarily determines the cell width. 197) The FP describes the pitch of active channels in the fin-FET device and is a strong contributor to performance scaling. 197) Recent trends in these design parameters are summarized in Table III. The 193 nm immersion lithography can resolve patterns with the 48 nm MP, which is achieved by the LELE technique of multiple exposure patterning. The SADP technique of sidewall image transfer double patterning achieved a 40 nm MP with a single orientation. The 40 nm GP is seen as the electrostatic and manufacturability limit for fin-FET devices. 197) A 24 nm FP is the approximate manufacturability limit for HAR fins in a fin-FET device. 201) The limit of GP scaling (the CPP) using SADP is 40 nm. 202) At this CPP, the gate length is ∼12 nm. Namely, 40 nm CPP manufacturing is at present limited by the process technology for manufacturing 3D complex structures.

Transistor-level scaling
At the transistor level, Alioto reported that the cell height affected the layout density in the physical layout design of fin-FET standard cells. 203) The cell height varies from 10 to 16 tracks, and an increased fin height permits reduction of the cell area. The fin height is a powerful parameter for improving the fin-FET layout density for any type of device and fin-FET manufacturing technology. 204) When shrinking the transistor dimensions, parasitic load involving capacitances and resistances must be considered to improve electrical performances. Parasitic resistances are gate resistance, contact resistance, and source=drain (S=D) series resistance. 204) The parasitic capacitances in fin-FETs have been analyzed in a number of studies. 205) A multigate fin-FET structure requires significant attention to the parasitic capacitances, that is, fringe capacitances by fin sidewalls, associated with 3D fins, multigates, dummy gates, and trench contacts. 205) The fringe capacitances are calculated by the addition of gate-tocontact, inner-gate-to-fin, and outer-gate-to-fin components. 206) The parallel plate capacitance is S=D diffusion along the gate sidewall and fin tops. 206) The overlap capacitance originates from an overlap between the S=D region and the gate. 206) The parasitic capacitance between the gate and contact is a very important contributor to the power-performance tradeoff and is mitigated by very low k materials or partial airgap spacer technology. 207) The contact resistivity component is also very important and is mitigated by significant increases in the source and drain surface doping and increasing the effective mass of the contact metal to make the contact quasi-ohmic and reduce interface carrier scattering. 208) In metal gate integration (RMG), the gate length requires very thin barrier metals with a thickness thinner than 2 or 3 nm and multiple threshold voltage (V t ) schemes that do not involve increases in barrier thickness. 209) Although patterning solutions exist, crossing the 40 nm CPP barrier is a daunting proposition from economic, yield, device performance and process control standpoints and quite possibly may not happen.

Cell-level: Circuit density scaling and DTCO
The greatest challenge in modern very large scale integration (VLSI) design is not in designing the individual transistors but rather in managing the system complexity. 195) Digital VLSI design is often partitioned into five levels of abstraction: architecture design, microarchitecture design, logic design, circuit design, and physical design. 195) To deal with these interdependences, microarchitecture, logic, circuit, and physical design must occur in parallel to some extent. 195) DFM is a methodology for ensuring that a product can be manufactured repeatedly, consistently, reliably, and costeffectively by taking all the measures necessary, starting at the concept stage of a design and implementing these measures throughout the design, manufacturing, and assembly processes. 210) The bleak prospect that device CD downsizing will stop is alleviated by the fact that circuit area scaling is enabled by several constructs (scaling boosters) at the circuit level that allow the reduction of the standard cell size through a reduction of the number of metal tracks. The power performance trade-offs in the implementation of such constructs constitute, in essence, a reason for DTCO. Examples of scaling boosters include single-diffusion breaks, self-aligned gate contacts, fin-cutting sequences (metal cutting), super-vias (for dense Mx routing), self-aligned blocks, and fully aligned vias.
Diffusion breaks refer to the space separation between two active device regions, where two dummy gates separate the two active regions, and the diffusion area is the silicon (non-isolation) region. 197) This provides a process window to tolerate CD variation in shallow trench isolation (STI) and gate-to-STI misplacement; however, the STI dimension needs to be very narrow so that the fin ends of adjoining  fin-FETs can tuck under one narrow dummy gate, even under worst-case misalignment. 197) Patterning and etching such a narrow STI are very difficult and the narrow STI CD can lead to high device leakage due to poor isolation. 197) Self-aligned contact (SAC) of gates and the S=D is also challenging. In the older planar technology, the gate pitch was relaxed such that S=D contacts and gate contacts could easily be placed next to each other without causing any shorting risk. 197) SAC mitigates the issue of S=D contact to gate shorts by fully encapsulated the gate metal with a dielectric spacer and gate cap. 197) The "fin cut first" and "fin cut last" schemes differ in the sequencing of dummy fin removal. 197) The "fin cut first" scheme defines the cut on the fin hard-mask level such that only one RIE step is needed to form the final fin shape. This sequence makes the isolation process simpler by requiring only a single oxide void-free "gap fill" and planarization. 197) Issues such as the complexity of the cut etching, the patterndependence of dielectric deposition, and the difficulty of chemical-mechanical polishing (CMP) arise from the nonuniformity of the pattern density. The "fin cut last" scheme, as the name implies, removes the dummy fins after the final fin image is etched into the substrate. This means that the fin has to be cut after the isolation process, which requires an additional isolation process after the fin cut. Therefore, the fin cut last scheme requires a larger number of process steps than the "fin cut first" scheme. As the fin is cut across the full topography of the final fin structure in the "fin cut last" scheme, cut mask misalignment can lead to spikes in the residual dummy fins. 197) Downsizing of ICs requires dimensional scaling from previous nodes for standard cell and custom logic requirements, and high-yield, low-cost integration schemes. 211) The reduction of cell area can be achieved by fully selfaligned gate contact, which makes the gate contacts over the active region, instead of conventional placement of gate contact outside of the diffusion area. 211) The self-aligning technology can be introduced at all levels, such as the frontend-of-line (FEOL), middle-of-line (MOL), and back-end-ofline (BEOL). Sherazi et al. reported boosting technology for a low-track-height standard cell design in the N7 node. 211) Some of these constructs are needed to scale the number of metal tracks per standard cell down to five or even four, as shown in Fig. 11. More innovative schemes such as buried power rails can be powerful enablers of area scaling without decreasing the CPP.

STCO for merging cross-point devices for logic and non-volatile memory
The "one device fits all needs" era is coming to an end, and a clear contender for replacing today's Si-based CMOS technology seems to elude us. In the longer term (10-15 years), we believe that the most promising progress in increasing functionality per unit cost will be through STCO for maximum system performance.
A recent example is Imec's resistive random access memory (RRAM)-based synaptic processing unit 212) optimized for machine learning applications. Through smart system-level partitioning, one can optimize system components with the most suitable technology. The Imec system was developed through low-cost 3D technologies and monolithic 3D integration. A variety of new material-based devices also have the potential to increase functionality at the system level by co-integration in the BEOL processing to fabricate interconnects with standard Si-based technology.
More disruptive technologies, such as the proposed nanofabrics, may allow the STCO-driven hybrid (functional) scaling trend to continue. The volume requirements in application domains will provide economies of scale that will justify this hybrid scaling approach.
The traditional standard-cell based design methodologies rely on a large library of standard cells to synthesize the logic of the design. As the cells are placed next to each other, a large number of layout patterns are created as each abutment of two cells has the potential to generate a new pattern neighborhood at the cell boundary. Although regular design methods are being adopted in the industry, the practices defined so far do not sufficiently restrict the number of layout patterns, especially at the edges of cells. Such macro-regularity for logic can only be enabled by carefully designing the edges of all cells. The regular design fabric and templates, which are introduced in the next subsection, specify the allowed layout constructs and layout neighborhoods using a completely prescriptive approach to IC layout design. 213) It is not easy to enforce all the pattern constraints desired by the regular design fabric by providing a grid-based design infrastructure to designers. 213) To ensure macro-regularity and enable efficient designs using regular design fabrics, we propose to add a level of abstraction between the standard cells and the regular design fabric, which we call logic templates. 213) Also, any memory architecture emerging to displace the NAND and DRAM incumbents must have a similar feature density. The tremendous number of features on a wafer also makes it critical that the statistical process capability also scales with each node.
New memory technologies, such as 3D cross-point (3DXP), also require the application of pitch multiplication and HAR etching technology to enable the targeted bit densities and high manufacturing volumes. These new memory technologies, similarly to 3DXP, also have unique dry-etching process challenges.

New materials, novel devices, and novel device constructs
One key enabler of the scaled gate length is the NW-based  device architecture 214) that allows optimal gate electrostatic control; a less electrostatically effective variant is the nanosheet (NS)-based device architecture, although the NS device architecture has the benefit of increased drive currents per unit area. 215) In addition, downsizing the CPP beyond 40 nm would require either a transition to EUV-based SADP or self-aligned quadruple patterning (SAQP), an increase in the number of NWs or NSs in the device stack, and extreme parasitic load mitigation solutions, 216) including the implementation of a full airgap spacer.
A steep on=off current transfer curve is required. Highmobility materials (Ge and III=V) have been hailed for years as candidates for replacing Si in scaled devices. However, advances in Si technology, the advent of NW and NS devices, and the many issues that plague high-mobility materials (leakage, defects, low temperature budgets, and cost) make their introduction less and less likely. A SiGe p-channel FET (pFET) or the introduction of stress in the n-channel through the use of strain-relaxed buffer substrates, shows promise for fin-FET devices; 217) however, their use is questionable in the NW=NS context.
Moving beyond traditional fin-FET devices, we see vertical FETs (VFETswhere the device channel is vertical) or complementary FETs (CFETswhere NWbased P and N devices are stacked on top of each other) as contenders to extend circuit area scaling (Fig. 12). 218) These devices are being built using mostly existing semiconductor technology (based on Si or SiGe). Although some innovations, such as nanotubes, are required, so they allow continued scaling through extreme gate shrinking. For example, VFET devices can be the most effective way of scaling static random access memory (SRAM), and III=V materials can provide the best figures of merit for the analog parts of a chip. By co-integrating these components in the most cost-effective fashion with standard Si-based logic, we can optimize the system functionality.
The 2D-material-based devices and spin-based devices also have the potential to increase functionality at the system level. Due to the employment of low-temperature fabrication, such 2D-material-based devices can be inserted in standard BEOL processing, and they offer the potential for stacking in a layered fashion. 219) Another class of devices involving spin propagation is also a potential candidate for co-integration with standard logic. 220)

Future challenges
We stress that atomic layer processes will continue to improve the CD uniformity at the bottom of HAR features. In 1992, Gottscho et al. discussed macroscopic CD uniformity. At that time, RIE lag resulted from microscopic transport phenomena within a single feature while microloading referred to a local dependence of the etching rate on the pattern density for identical features. 89) The microloading is caused by the same mechanisms as those cause macroloading in one type of ARDE. 221) The ARDE mechanisms were categorized into (1) Knudsen transport of neutrals, (2) ion shading, (3) neutral shadowing, (4) differential charging of an insulating microstructure, (5) field curvature near the conductive topography, (6) surface diffusion, (7) bulk diffusion, and (8) image force deflection. 131) Fujiwara et al. pointed out that the etching rate was influenced by the transport of ions and neutrals inside HAR features. 35) Knudsen transport provides a simple description of the neutral transport that occurs in HAR features; that is, the neutrals travel without colliding with reflections at the wall, giving them a cosine angular distribution. As a result, the neutral transport rate is obtained by molecular diffusion and the surface sticking coefficient (inversely related to the scattering coefficient). Accordingly, neutrals with thermal motion having randomly directed incidence at the top entrance to HAR features have a net flux into the feature with thermal velocity given by where k is Boltzmann's constant, T is the temperature, and m is the atomic or molecular mass. Then, during the transport, the sticking of neutrals determines the neutral flux to the bottom of HAR features. Also, bulk or surface diffusion of the sticking neutrals may need to be taken into consideration. Briefly, the reduced sticking of neutrals at the sidewalls of HAR features results in a higher flux of neutrals that reach the bottom. The ARDE properties are crucial for understanding the effects of gas and surface temperatures. For spontaneous etching regimes, sidewall passivation is considered by exploring low-temperature processes. In contrast, neutral starvation may possibly be solved by high-temperature processes. Nevertheless, the reaction probability for the targeted etching reaction and the net fluxes of reactants reaching the bottom determine the etching rates and ARDE characteristics. However, we emphasize again that self-limiting processes take advantage of the independence of macroscopic and microscopic loading effects. Much work remains for developing revolutionary methods that overcome these problems.
Returning to the starting point, we reconsider the surface etching reactions occurring at an HAR hole bottom (Fig. 13). In accordance with RIE behavior, radicals and ions synergistically contribute to the formation of etching products. Ohiwa et al. argued mechanisms of etching rates for bottom on reflections at hole sidewall during etching with ion transport inside HARC. 106) As discussed in Sect. 3.3, the IED and IAD with higher bias power is becoming a critical technology and a new boosting technology is necessary.
For understanding of the atomic-level processes, information about the details of these processes remains insufficient, because dynamical changes in etching state under determined by a stochastic process that a future state depended on the present state, i.e., non Markovian-process. To control the etching process as a system, final state should be causal deterministic from initial states. Namely, of great interest is the nonequilibrium dynamics of the etching processes. Similarly consider the dynamics as a system, a response time with or without a relaxation determines characteristic frequency. Note that self-limiting processes become free from this frequency and robust in space and time. In a essence meaning, the atomic-level and self-limiting reactions contribute on taking advantages for improving any uniformity, namely, achieving a temporal-and spatial-variation-free (adaptive) control. 222) A remained main problem is how to know a present state of the etching system. Together with actual observations of behaviors of the system variables at real time, a mathematical description of the dynamics may solve strictly or probabilistic causal states that represents, for example, etching rates, etched profiles, CD uniformities, and forth. We can specify a local response within the system on the basis of principles or theories. Hence, system-scientific approaches are necessary to understand mechanisms of the atomic-level deposition and etching processes. More simply, it attempts that computational results provide us with a basic understanding of complex reactions; however, they have not been verified by experimental results. Currently, the IEDs and IADs are obtained by a consensus of the importance of CD uniformity at an HAR trench or hole bottom. The Kushner group reported computational results for IEDs and IADs in plasma etchers operated at multiple frequencies. [223][224][225][226][227][228] However, charging effects at the HAR feature bottom are very complicated. Charge build-up inside insulating HAR features may distort the ion trajectories, causing ions to strike the sidewalls. This is essentially caused by electron shading of the HAR features because the electron flux is isotropic. To solve this problem, the anisotropic flux of electrons or negatively charged ions should be considered. Furthermore, when charges between electrons and ions are balanced at the bottom, an electropositive potential develops there. Economou and coworkers reported electrostatic lenses that were fabricated by constructing a surface metal plate and substrate and these lenses were achieved by electrostatic focusing of ions inside HAR feature sandwiched two electrostatic electrodes, realizing the patterning of nanofeatures, they called as nanopantography. 229,230) Their collimating method with a monoenergetic ion-beam has attracted great attention also for the purpose of IED and IAD contol. The resultant ion flux needs to increase at the wafer-biasing voltages. Further study of the control of CD uniformity at the HAR feature bottoms is still required with an emphasis on charging, absorbates, and redeposition of by-products.
We presented some state-of-the-art examples to demonstrate that progress can be made by coordination among theory, computation, and experiments (Fig. 14). To do this, fundamental data are indeed necessary. For ion-induced reactions on an etched surface, the etching yield per incident ion is basic information that we need to have. In recent research, Karahashi

Theory Computation
Chamber

Hierarchy
Virtual experiments w/AI supports  region without dissociation (HBr + , Cl 2 + , and O 2 + ). 235) Very recently, they predicted the dissociation pathways for a hydrofluorocarbon molecule of 1,1,1,2-tetrafluoroethane (HFC-134a), 236) and cross-section sets for electron collision induced reactions were provided by the combinationapproach of swarm experiments and numerical procedure, as reviewed by Petrovic and coworkers. 237) Kawaguchi et al. reported computationally estimated electron transport coefficients in water vapor, fitting to partially-obtained experimental data using simulations with cross section sets and Boltzmann equation analysis. 238) Further advances for the coordination will be achieved with new experimental and theoretical techniques.
Our personal view is that new ways can be found to confirm quantitative agreement between virtual and actual experiments. To realize this approach, we need to practically exploit an interdisciplinary environment involving physics theorists and information scientists. Moreover, the actual mechanisms of atomic layer reactions are challenging to elucidate. Artificial intelligence (AI) and machine learning systems will support the automation of discovering optimal conditions to find solutions to the issues described here (Fig. 14). An etching recipe that is conducting in the chamber results to obtain some processed variables such as deposi-tion=etching rates, conformality, material selectivity and profile dependences. To discovery an optimal recipe, hierarchal levels should be solved by theoretical, numerical, and experimental approaches. The levels comprise of gasphase reaction-chemistry and plasma physics inside the reaction-chamber. [239][240][241][242] In virtual optimization, for example, numerical computations require fundamental data stored database to perform particle-in-cell (PIC) simulations and the Boltzmann equation on basis of theories in fluid mechanics, electron dynamics. Experiments can evaluate the simulated results. Feed-back and feed-forward in the cycle of computation and experiments will realize to construct a virtual experiment-environment and can afford to discovery an optimum with the AI automation. For realization of the automation, we stress again that fundamental data sets such as cross-sections for electron-molecules binary collisions, absorption coefficients of atoms=molecules on plasma-processed surface and etching yield of target materials for ion irradiations plays key role in attempts of the searching of a new recipe and applications of the optimization of recipes. In the future, AI will support the opening of a new era for emerging dry processes.

Conclusions
We have discussed recent advances in fabrication technologies using atomic layer processing for plasma etching of HAR features in semiconductor manufacture. We reviewed HAR etching technologies with respect to (1) CD scaling, (2) macroscopic CD uniformity, and (3) CD uniformity at the bottom of features. We also outlined the major challenges for future research on the atomic layer fidelity of dry etching processes.