Design and analysis of nanowire p-type MOSFET coaxially having silicon core and germanium peripheral channel

In this work, a nanowire p-type metal–oxide–semiconductor field-effect transistor (PMOSFET) coaxially having a Si core and a Ge peripheral channel is designed and characterized by device simulations. Owing to the high hole mobility of Ge, the device can be utilized for high-speed CMOS integrated circuits, with the effective confinement of mobile holes in Ge by the large valence band offset between Si and Ge. Source/drain doping concentrations and the ratio between the Si core and Ge channel thicknesses are determined. On the basis of the design results, the channel length is aggressively scaled down by evaluating the primary DC parameters in order to confirm device scalability and low-power applicability in sub-10-nm technology nodes.


Introduction
Ge is rapidly regaining considerable interest as an important semiconductor material for applications to high-speed lowpower integrated circuits (ICs). Ge has approximately 4.2-and 2.6-fold higher bulk hole and electron mobilities, respectively, than Si, and a high Si CMOS processing compatibility. [1][2][3] In particular, Ge is a promising channel material for p-type metaloxide-semiconductor field-effect transistors (PMOSFETs) since its hole mobility is the highest among the well-known group IV and III-V semiconductor materials that have been used for device fabrications [1]. Although Ge is an indirectbandgap material, it has a higher radiative recombination probability than Si, since Ge has a local minimum at k = 0 in the momentum space, which improves the probability of spontaneous emission. The electron affinities of Si and Ge are 4.0 and 4.05 eV, respectively, and the energy bandgap (E g ) of Ge is about half that of Si. The smaller E g of Ge allows further scaling of drive voltage. 4) Also, its relatively low melting point leads to the low-temperature activation of source=drain (S=D) dopants at 400-500°C, 5,6) which facilitates the formation of shallow junctions and necessitates a high-κ=metal gate stack that is usually constructed at a low thermal budget. Owing to these virtuous features, there has been consistent effort in realizing both electron and optical devices based on Ge including nanowire Ge PMOSFETs, Ge-on-insulator (GOI) MOSFETs, Ge light-emitting diodes (LEDs), and lasers. 3,4,[7][8][9][10][11][12][13] To obtain a GOI substrate as the platform for Ge electronics, a Ge condensation technique has been employed as illustrated in Fig. 1. [14][15][16][17][18][19] Although a silicon-oninsulator (SOI) substrate is a prerequisite in obtaining the GOI substrate through the condensation technique, SOI can be replaced with bulk Si in preparing the starting material to reduce the cost. 20,21) By either the partial or whole condensation of Ge out of the SiGe alloy epitaxially grown in the geometrically confined Si area, the active regions in various shapes fabricated from Ge can be constructed easily.
In this work, a novel nanowire Ge PMOSFET coaxially having a Si core and a Ge peripheral channel is proposed and optimally designed. The Ge channel can be formed through a Ge condensation technique on a Si nanowire. Owing to the benefits from the device structure and channel material, a stronger gate controllability, a higher current drivability, and a more robust immunity against short-channel effects (SCEs) are expected from the proposed device. 22,23) The nanowire Ge PMOSFET is optimally designed by rigorous device simulations, 24) and its potential applicability in sub-10-nm logic technology nodes is evaluated. Content from this work may be used under the terms of the Creative Commons Attribution 4.0 license. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. Fig. 1(a). Although the E g of Si and Ge are 1.12 and 0.66 eV, respectively, at room temperature, the large difference in E g is mostly projected to the valence band offset (VBO) since Si and Ge have very small electron affinity differences of 4.0 and 4.05 eV, respectively. By making use of these properties of Si and Ge heterojunction, holes can be effectively confined in the Ge region, which will be the channel material with high hole mobility. By electrical isolation between Si and Ge through the large VBO, it is not substantially probable that the Si core acts as a leakage path for hole current conducting through the Ge channel.

Device structure and simulation approach
To obtain simulation results with higher accuracy and reliability, various models were adopted simultaneously, including the vertical and parallel electric-field-dependent mobility model, concentration-dependent mobility model, band-to-band tunneling model developed by Hurkx et al., 25) bandgap narrowing model, Fermi-Dirac statistics, and quantum-mechanical model. A two-dimensional (2D) rectangular structure was constructed first and rotated to build a threedimensional (3D) structure having cylindrical symmetry to include more supporting models available only in 2D simulations and obtain a better convergence of numerical calcula-tions. To suppress the S=D parasitic resistance and meet the gate pitch requirement, the distance between the S=D contacts to the gate edge was fixed at 20 nm. The saturation currents obtained from the design work are higher than those suggested by the most recent technology roadmap (ITRS), as will be shown in a later section. Furthermore, empirical saturation velocities of electrons and holes in Ge were employed in the simulations for a higher reliability. 26,27) The S=D doping concentration was optimized in terms of DC and AC parameters including on-(I on ) and off-state (I off ) currents, current ratio (I on =I off ), drain-induced barrier lowering (DIBL), subthreshold swing (S), and transconductance (g m ). The simulated device channel length (L g ) and Si:Ge thickness ratio were fixed at 50 nm and 5 nm : 5 nm, respectively. The p-type (p + ) S=D doping concentration was controlled from 10 16 to 10 20 cm −3 for the optimization. The doping concentration of the n-type channel was fixed at 10 15 cm −3 . I on and I off are defined as the currents where the gate voltage (V GS ) is equal to −0.85 and 0 V, respectively, at the on-state drain voltage (V DS ). The drive voltage (V DD ) of −0.85 V has been assumed in accordance with the requirements for low-power (LP) and high-performance (HP) applications in the most recent technology roadmap. 28) I on =I off current ratio was calculated to evaluate logic switching characteristics. There have been two conditions of drain biases: one is low at −50 mV and the other is high at V DS = V DD = −0.85 V in tracing the transfer curves. Threshold voltage (V th ) was extracted by the constant current method at I D = 10 −8 A, and DIBL was obtained as the difference in V th at high and low V DS values. S was calculated to be the reciprocal of the maximum slope in the subthreshold region. Furthermore, to have a glimpse of the AC performance, the maximum available transconductance (g m,Max ) values was extracted under each S=D doping condition. Although the g m of a MOSFET is extracted at a certain operating point in many cases, how large g m can be possibly obtained from a device over a wide range of gate operating voltage without pinning to a specific V GS may provide a higher practicability for general purposes, particularly when it comes to an unknown device. Thus, the maximum available g m (g m,Max ) is more importantly considered in this work.
The Si:Ge thickness ratio was optimized through device simulations. The doping concentration of 5 × 10 18 cm −3 was chosen from the permissible range in optimizing the Si:Ge thickness ratio considering the convenience in fabrication and the high device reliability. Here, the total thickness of Si and Ge regions was fixed at 10 nm for securing a small foot-print. Simulations have been performed with the variation of Ge thickness from 0 to 10 nm by 1 nm steps. In the case of a 10nm-thick whole Si channel, since the device is already completely turned off at V GS = −0.4 V, the transfer curve was extracted by sweeping V GS from 0.2 down to −1.5 V. The simulated device L g was fixed to be 50 nm. The Si:Ge thickness ratio was optimized in terms of DC and AC parameters including I on and I off , I on =I off , DIBL, S, and g m,Max in the same manner as that in which the first simulations were performed.
Finally, L g was controlled from 200 down to 7 nm under the thickness condition of Si : Ge ¼ 2 nm : 8 nm, selected from the permissible thickness ratio range. By carrying out the series of simulations, the scalability of the proposed device was closely investigated through I on and I off , I on =I off ,  DIBL, S, and g m , while emphases were made on performance optimization in the first and second tasks. Figure 3 shows the I D -V GS transfer curves of the proposed nanowire Ge PMOSFETs with different S=D doping concentrations at V DS = V DD = −0.85 V. The S=D doping concentrations are 10 16 , 10 17 , 10 18 , 5 × 10 18 , 8 × 10 18 , 10 19 , 2 × 10 19 , 3 × 10 19 , and 10 20 cm −3 . A very low doping concentration is not capable of drawing a high I on and also an excessively high doping concentration is not desirable for the suppression of I off . Figures 4(a) and 4(b) show I on and I off and I on =I off , respectively. For a better current drivability, the S=D doping concentration must be higher than 5 × 10 18 cm −3 , and for a lower I off , a doping concentration of 10 19 cm −3 or lower should be designed in order to minimize the leakage caused by band-to-band tunneling. The maximum I on =I off ratio is obtained at the doping concentration of 5 × 10 18 cm −3 . I on increases faster than I off as the doping concentration increases until reaching 5 × 10 18 cm −3 , while I off increases faster than I on above this point, which provides an optimum condition for maximizing the I on =I off ratio at 5 × 10 18 cm −3 . Figure 5 depicts DIBL, where the reference current for extracting V th 's by the constant current method is I D = 10 −8 A. As can be confirmed by Figs. 4(a) and 4(b), I off becomes impermissibly high at the S=D doping concentration of 10 20 cm −3 . The mathematically extracted DIBL is impractically large, and thus, it is determined that the S=D doping concentration is required to be no higher than 3 × 10 19 cm −3 for maintaining a small DIBL of around 30 mV=V. Figure 6 demonstrates S as a function of S=D doping concentration. S does not notably degrade as the doping concentration increases but is tied to a plausibly small value near 60 mV=dec, the theoretical limit in the presence of thermionic emission at 300 K, at doping concentrations of 10 19 cm −3 and below. S (mV=dec) is defined as 29) S ¼ ln 10 Á mkT q

Optimization of S/D doping concentrations
Here, k is the Boltzmann constant, T is the temperature in K, and q is the unit charge in C. C dm and C ox are the depletion and gate oxide capacitances seen by the gate, respectively. The radical extension of depletion regions from S=D ends toward the channel center occurs as the S=D doping concentration increases, which makes the channel less sensitive to the gate, and the change in depletion length by V GS decreases. The thinner depletion by the gate increases C dm and the swing becomes worse as shown in Fig. 6 and the radical degradation is observed above 10 19 cm −3 . g m,Max shows a monotonic increase with S=D doping concentration, as shown in Fig. 7. A high g m,Max reaching 10 −4 S would be warranted at 10 18 cm −3 and above. The first derivative of the I D -V GS curve is located at V GS values smaller than −0.85 V (|V GS | < 0.85 V) for the devices with S=D doping concentrations below 10 19 cm −3 . However, above this doping concentration, there is no local maximum in the g m -V GS curve but g m monotonically increases

Optimization of thickness of Ge peripheral channel
Considering the variations of the DC and AC parameters of the proposed nanowire Ge PMOSFET including I on , I off , I on =I off , DIBL, S, and g m , the optimized device performance is expected in the S=D doping concentration range between 5 × 10 18 and 10 19 cm −3 at a thickness ratio of Si core : Ge channel ¼ 5 nm : 5 nm. Here, the permissible S=D doping concentration is chosen to be 5 × 10 18 cm −3 from the design window for optimizing the ratio between the Si core and Ge channel thicknesses at the given total semiconductor nanowire radius of 10 nm. Taking the higher process viability and lower performance deviation into account, the lower limit of 5 × 10 18 cm −3 has been selected as an optimal S=D doping concentration. Transfer curves from the devices with different Ge channel thicknesses are shown in Fig. 8 with the S=D doping concentration of 5 × 10 18 cm −3 at V DS = −0.85 V. The total nanowire radius (Si core + Ge peripheral channel thicknesses) and L g are fixed to be 10 and 50 nm, respectively. The device with the whole Si channel (Ge 0 nm: Si 10 nm) has a lower I off (I D at V GS = 0 V) owing to the lower probability of band-toband tunneling by the relatively large E g of Si (1.12 eV) compared with that of Ge (0.66 eV). On the other hand, its current drivability is lower than that in the case where the Ge channel is beneath the gate oxide since the V th of the whole-Si-channel device significantly shifts toward the left-hand side, which is also not desirable for realizing low-voltage operation. The nanowire PMOSFETs with Ge peripheral channels show two decades higher I off than that of the whole-Si-channel device, and it is confirmed from Fig. 8 that a larger portion in Ge thickness has an effect of reducing I off . Figure 9(a) depicts I on along with I off with increasing Ge thickness. I on monotonically increases and saturates above the Ge thickness of 3 nm as shown in the figure. At the same time, I off decreases in this region with Ge thickness. To achieve a higher current drivability and better switching characteristics, Ge thicknesses of 3 nm and above would be desirable in the design optimization, as can be confirmed from Fig. 9(a). The I on =I off ratio in the case of embedding the Ge channel is prominently higher than that in the case of employing only Si in the nanowire channel and it increases with Ge thickness ratio as depicted in Fig. 9(b). The gate metal workfunction is fixed to be 4.08 eV for a fair comparison and an efficient simulation design, and the corresponding metal can be Al having a clean CMOS processing compatibility. Figure 9(c) shows the potential contours in the devices with Ge thicknesses of 3 nm (left) and 8 nm (right). Compared with the case of 3 nm thickness, that of 8 nm demonstrates a high potential in the Ge channel region. The high potential originates from the workfunction difference between the poorly doped Ge channel and the gate. As shown in Fig. 9(d), holes are the majority carrier making up the offstate current. Thus, a higher potential makes the holes in the source junction see a higher potential energy barrier in the channel direction, and the source hole injection into the channel by diffusion becomes more difficult in the case of the 8-nm-thick Ge channel. The fundamental reason for this lies in the fact that Ge has a higher electrical permittivity than Si, by which Ge experiences smaller potential gradients in the radial direction. Figure 10 plots DIBL as a function of Ge thickness. DIBL is kept to be as small as near 13 mV=V, which reveals that the device structure and material design present strong immunity against the SCEs. Also, the variance in DIBL is confined to a small window, within 5 mV=V, over the entire controlled Ge thickness range. Figure 11 shows S as a function of Ge thickness, where the distribution is concentrated plausibly near 60 mV=dec, the theoretical lower   limit in the drift-diffusion carrier transport, for all the simulated Ge thicknesses up to 10 nm. g m,Max is depicted as a function of Ge thickness in Fig. 12. g m,Max demonstrates a monotonic increase in the entire region, except in the case of the whole-Si-channel device, and the Ge thickness for an optimal design is suggested to be above 5 nm where g m,Max higher than 40 µS is obtained.
Obtaining a Ge channel thicker than 5 nm without dislocation or defect sites can be challenging since the critical thickness of Ge on Si is around 5 nm. 30) However, the proposed device in this work can be fabricated by Ge condensation with only minimal dislocation and defect formation. 14) Also, the critical thickness of the Ge epitaxy layer on the Si nanowire structure is enhanced and the stress decreases as the Ge layer becomes thicker. 31) Owing to the lack of systematic experiments on critical thickness in the case of condensation processing, it can be safe to reference the results of the epitaxial growth of Ge on Si, and a problematic thickness can be discarded in an actual device realization. Since the nanowire channel surface is basically omnidirectional, the highly angle-dependent strain effects on the on-and off-state current characteristics through the band structure modification become complicated. The simulation results in this work can provide guidelines in designing the device performance without fully including the interfacial status and the strain effects at this moment. Moreover, studies on more realistic phenomena affecting the device performances should be carried out as one of the related future works.

Evaluation of length scalability of the proposed Ge PMOSFET
From the results of the optimization of Ge thickness, the common set of thickness ranges determined by respective parameters indicates that channels of 5 nm thickness and above should be permissible in designing the proposed device. Si core : Ge peripheral channel ¼ 2 nm : 8 nm is chos- en to ensure a high g m,Max to evaluate the length scalability down into the sub-10-nm regime. The optimum S=D doping concentration is constantly assumed to be 5 × 10 18 cm −3 . Figure 13 shows the transfer curves from the devices with different L g 's ranging from 200 down to 7 nm (200, 100, 50, 30, 20, 10, and 7 nm). As L g decreases, the transfer curves tend to be right-shifted by SCEs including DIBL and degradation in S as examined previously. The same set of device parameters is investigated as L g is scaled down. Both I on and I off increase as L g decreases as shown in Fig. 14(a). The I on =I off ratio is invariant with L g from 200 down to 50 nm but remarkably rolls off from 50 to 7 nm, generally showing a monotonic decrease as shown in Fig. 14(b). Normalized saturation currents at each L g are extracted as depicted in      Table I. Also, the first and second rows in Table II show the targeted saturation current of the Ge multigate (MuG) PMOSFET and the ratio between a saturation currents of the Ge MuG NMOSFET and PMOSFET. A simple calculation leads to the saturation current requirement of the Ge MuG PMOSFET as inserted in the third row. It is confirmed from the tables that the proposed device in this work satisfies the requirements. Also, it is revealed that the S=D parasitic resistances have been well suppressed and do not become a substantial hindrance in meeting the requirements. Figure 15 depicts DIBL as a function of L g , as the difference between V GS 's for I D = 10 −8 A at low and high V DS values of −50 mV and −0.85 V divided by ΔV DS . Although DIBL increases as L g decreases as can be predicted from the SCEs, a small DIBL not exceeding 100 mV=V can be expected even at L g = 7 nm. A small S near 60 mV=dec is obtained from the device having L g = 200 down to 30 nm and sharply increases below 30 nm as demonstrated in Fig. 16. Figure 17 depicts g m,Max as a function of L g , where g m,Max is locally maximized to be 44.78 µS at L g = 30 nm. g m in the strong inversion mode is defined as follows with an assumption of constant effective mobility: 32) Here, W is the channel width and C ox is the oxide capacitance. The smaller g m,Max in the region of L g < 30 nm is attributed to the weaker gate controllability over the channel and the smaller carrier responsivity to the gate. For the region of L g > 30 nm, decreasing g m,Max results from the lower current drivability inversely proportional to L g as can be predicted using Eq. (2). However, g m,Max is generally plotted to be higher than 30 µS and g m,Max = 31.95 µS is obtained at L g = 7 nm.

Conclusions
In this work, we proposed and optimized a nanowire Ge PMOSFET having a Si core and a Ge peripheral channel by device simulations. The criteria for device optimization were primary DC and AC parameters including I on , I off , I on =I off ratio, DIBL, S, and g m . The S=D doping concentration and Si:Ge thickness ratio were optimized, and then, the scalability of the proposed device was closely investigated by scaling down the channel from 200 down to 7 nm. The optimal S=D doping concentration was found to be 5 × 10 18 cm −3 at V DD = −0.85 V and a Ge channel thicker than 5 nm out of a total Si + Ge thickness of 10 nm was revealed to be desirable for preparing a set of better DC and AC parameters. The proposed nanowire Ge PMOSFET with a channel length of 7 nm demonstrated permissible device performance characteristics including I on = 1.58 × 10 −5 A, S = 89.5 mV=dec, and g m,Max = 3.195 × 10 −5 S, which supports the potential for LP and HP applications in sub-10-nm technology nodes.