Suppression of reverse recovery surge voltage of silicon power diode by adjusting trap energy levels through local lifetime control

Yusuke Yamashita; Satoru Machida; Takahide Sugiyama

doi:10.7567/JJAP.53.04EP14

1. Introduction

Silicon power diodes are widely used in applications such as home electric appliances and hybrid vehicles, and it is increasingly demanded that their reliability be improved. Reverse recovery surge voltage is one important reliability issue, because surge voltage causes avalanche breakdown and electromagnetic interference noise.¹^–⁴⁾ Hence, methods of suppressing the reverse recovery surge voltage of silicon power diodes are being investigated.

During the on-state of a diode, minority excess carriers are injected into the drift region from the anode and cathode layers. In the transition from the on-state to the off-state, excess carriers are removed from the drift layer, producing a reverse recovery current.¹^,⁵^,⁶⁾ A high current change rate (di/dt) and a large parasitic inductance cause high surge voltage.¹⁾ The di/dt value is determined by an excess carrier distribution in the drift region immediately before a reverse recovery.¹^,⁶⁾ Nowadays, there are two techniques commonly used for obtaining an optimum excess carrier distribution. One is carrier injection control and the other is local lifetime control. For example, an emitter-controlled (EMCON) diode,⁷^,⁸⁾ the diode with controlled injection of back-side holes (CIBH),⁹^,¹⁰⁾ the merged PiN/Schottky (MPS) diode,¹¹^,¹²⁾ and other diodes¹³^–¹⁵⁾ are used in carrier injection control. On the other hand, noble metal atom diffusion and charged particle irradiation are used in local lifetime control.¹⁶^–²¹⁾

In previous studies, local lifetimes were controlled by localizing carrier traps. In other words, the carrier lifetime profile is generally controlled by adjusting the trap distribution.¹⁶^–²⁰⁾ However, in fact, reverse recovery characteristics are also affected by trap energy levels.²²^–²⁴⁾ We previously verified that variations in recombination rate due to the difference in trap energy level affect surge voltage.²⁵⁾ However, in our previous study, we investigated only a flat trap density distribution and did not consider local lifetime control.

Therefore, in this study, we clarify the effect of local lifetime control on the suppression of surge voltage through the adjustment of trap energy level, and develop guidelines for suppressing surge voltage through the design of silicon power diodes.

2. Methods

To determine the trap energy level that effectively suppresses surge voltage, we have to clarify the relationship among the surge voltage, the carrier lifetime, and the trap energy level.

First, the relationship between the carrier lifetime profile and the surge voltage was calculated by device simulation using the Sentaurus Device (Synopsys). We simulated the P+ N− N+ diode structure and carrier lifetime profiles shown in Fig. 1. τ_a and τ_c are the carrier lifetimes of the anode and cathode sides, respectively. It is assumed that τ_c is larger than τ_a, and that the carrier lifetime ratio is defined as τ_c/τ_a.

**Fig. 1.** Schematic model used for simulation.
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Second, the relationship between the carrier lifetime and the trap energy level was analyzed by theoretical analyses with the Shockley–Read–Hall (SRH) model.²⁶^,²⁷⁾ Table I shows a lists of the definition of symbols and parameters used for the calculation. Assuming a single trap energy level, the total recombination rate R_r in the N-drift region is expressed as

$\begin{equation} R_{\text{r}} = R_{\text{bulk}} + R_{\text{trap}}, \end{equation} \tag{ 1 }$

where R_bulk and R_trap are the recombination rate in the bulk silicon substrate and the recombination rate due to the trap, respectively. Under high injection conditions ( $p_{\text{n}} \gg n_{\text{i}}^{2},p = n$ ), R_bulk and R_trap can be approximated as²⁸^,²⁹⁾

$\begin{align} R_{\text{bulk}} &= \frac{pn-n_{\text{i}}^{2}}{\tau_{\text{p}}(n+n_{\text{i}})+\tau_{\text{n}}(p+n_{\text{i}})}\approx\frac{p_{\text{n}}}{\tau_{\text{bulk}}}, \end{align} \tag{ 2 }$

$\begin{align} R_{\text{trap}} &= \cfrac{\sigma v_{\text{th}} N_{\text{t}} (pn - n_{\text{i}}^{2})}{\biggl[n + n_{\text{i}}\exp \biggl(\cfrac{E_{\text{t}} - E_{\text{i}}}{kT}\biggr)\biggr] + \biggl[p + n_{\text{i}}\exp \biggl(\cfrac{E_{\text{i}} - E_{\text{t}}}{kT}\biggr)\biggr]} \\ &\approx\cfrac{\sigma v_{\text{th}} N_{\text{T}} p_{\text{n}}^{2}}{2\biggl[p_{\text{n}} + n_{\text{i}} \cosh \biggl(\cfrac{E_{\text{t}}- E_{\text{i}}}{kT}\biggr)\biggr]}. \end{align} \tag{ 3 }$

Table I. Definitions of symbols and parameters used for calculation.

Symbol	Definition	Symbol	Definition
R_r	Total recombination rate	N_t	Trap density
R_bulk	Intrinsic recombination rate	τ	Total carrier lifetime
R_trap	Trap recombination rate	τ_p	Intrinsic hole lifetime
p	Hole density	τ_n	Intrinsic electron lifetime
n	Electron density	τ_bulk	Intrinsic carrier lifetime
p_n	Excess carrier density	E_t	Trap energy level
n_i	Intrinsic carrier density	E_i	Mid band energy level
σ	Capture cross section	k	Boltzman constant
$v_{\text{th}}$	Thermal velocity	T	Temperature

From Eqs. (1)–(3), the following relationship among the excess carrier density p_n, the recombination rate R_r with various trap energy levels, and the total carrier lifetime τ in the drift region is established as

$\begin{equation} R_{\text{r}} = \frac{\sigma v_{\text{th}} N_{\text{t}} p_{\text{n}}^{2}}{2[p_{\text{n}} + n_{\text{i}} \cosh \{(E_{\text{t}} - E_{\text{i}})/kT\}]} + \frac{p_{\text{n}}}{\tau_{\text{bulk}}} = \frac{p_{\text{n}}}{\tau}, \end{equation} \tag{ 4 }$

where σ is the capture cross section, $v_{\text{th}}$ is the thermal velocity, N_t is the trap density, and τ_bulk is the intrinsic carrier lifetime in the bulk silicon substrate.

Finally, from these calculations, we investigate the trap energy levels that are effective for the suppression of the surge voltage.

3. Results and discussion

3.1. Device simulation analysis: carrier lifetime profile dependence of reverse recovery surge voltage

Figure 2 shows simulated forward current voltage curves of diodes with various carrier lifetime ratios τ_c/τ_a at a temperature of 300 K. Traps were not defined in this simulation. The average carrier lifetime was adjusted to match the forward voltage drop at 200 A/cm² for each lifetime ratio. Figure 3 shows the dependence of the hole density distribution on τ_c/τ_a. The position of the minimum carrier density is found at the center of the drift region when the carrier lifetime profile of the diode is flat (τ_c/τ_a = 1). This position moves toward the anode with an increase in τ_c/τ_a.

**Fig. 2.** Simulated current–voltage curves for various carrier lifetime ratios (T = 300 K).
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**Fig. 3.** Simulated hole density distributions for various carrier lifetime ratios (T = 300 K).
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Figures 4(a) and 4(b) show the calculated dependences of reverse recovery current and voltage waveforms, respectively, on τ_c/τ_a with an inductive load in a double-pulse mode. The reverse recovery waveform exhibited a soft recovery with an increase in τ_c/τ_a. Figure 5 shows the relationship between the surge voltage and the τ_c/τ_a obtained from Fig. 4. The flat carrier lifetime profile (τ_c/τ_a = 1) diode exhibited the highest surge voltage. The anode side lifetime τ_a decreased and the cathode side lifetime τ_c increased, resulting in a low surge voltage. Therefore, the surge voltage can be suppressed by increasing τ_c/τ_a.

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**Fig. 5.** Simulated carrier lifetime ratio dependence of surge voltage (T = 300 K).
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3.2. Theoretical analysis: trap energy level dependence of carrier lifetime profile

Figure 6(a) shows the schematic structure of a P+ N− N+ diode that we used for theoretical and numerical analysis models. The anode side trap density N_ta is ten times higher than the cathode side trap density N_tc in all analyses. To investigate the effects of various trap energy levels, N_ta/N_tc was maintained constant. Figure 6(b) shows a band diagram of a trap. We define the trap energy levels near the midpoint of the band gap as deep levels and those near the conduction or valence band as shallow levels.

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Figure 7 shows the correlation between the recombination rate and the excess carrier density, calculated with Eq. (4), in the cases of E_t − E_i = 0.1 eV (example of deep level) and E_t − E_i = 0.4 eV (example of shallow level). The trap density was adjusted to match the recombination rate at p_n = 4 × 10¹⁶ cm⁻³ for each trap energy level. It can be assumed that the diodes of the two trap energy levels have the same forward voltage drop at about 200 A/cm². Note that the slope of the E_t − E_i = 0.1 eV line is constant, whereas that of the E_t − E_i = 0.4 eV line varies with carrier and trap densities. This difference is due to a difference in the probability of carrier emission from a trap. The probability of carrier emission is proportional to the term n_i cosh{(E_t − E_i)/kT} in Eq. (4). This term increases exponentially with an increase in [E_t − E_i]. At deep levels, E_t − E_i is small, and the value of that term is negligible. In this case, Eq. (4) can be approximated as

$\begin{equation} R_{\text{r}} = \frac{\sigma v_{\text{th}} N_{\text{t}} p_{\text{n}}}{2} + \frac{p_{\text{n}}}{\tau_{\text{bulk}}}. \end{equation} \tag{ 5 }$

**Fig. 7.** Calculated correlation between recombination rate and excess carrier density (T = 300 K).
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Equation (5) indicates that the recombination rate is proportional to the excess carrier and trap densities. On the other hand, at shallow levels, the effect of that emission probability term cannot be ignored. This difference in slope makes the carrier lifetime dependent on multiple factors.

Because carrier lifetime is inversely proportional to recombination rate, it can be calculated as follows from Eq. (4):

$\begin{equation} \tau = \cfrac{1}{\cfrac{\sigma v_{\text{th}} N_{\text{t}} p_{\text{n}}}{2[p_{\text{n}} + n_{\text{i}} \cosh \{(E_{\text{t}} - E_{\text{i}})/kT\}]} + \cfrac{1}{\tau_{\text{bulk}}}}. \end{equation} \tag{ 6 }$

Figure 8 shows the correlation between the carrier lifetime and the excess carrier density, calculated from Eq. (6). In the case of E_t − E_i = 0.1 eV, the carrier lifetime is constant. In contrast, in the case of E_t − E_i = 0.4 eV, the carrier lifetime varies with the excess carrier and trap densities. This means that the delta of carrier lifetime between high and low trap densities in the case of E_t − E_i = 0.1 eV is constant, unaffected by the excess carrier density, and that this delta in the case of E_t − E_i = 0.4 eV changes with the excess carrier density.

**Fig. 8.** Calculated correlation between carrier lifetime and excess carrier density (T = 300 K).
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The carrier lifetime ratio τ_c/τ_a can be established from Eq. (6) as

$\begin{equation} \frac{\tau_{\text{c}}}{\tau_{\text{a}}} = \frac{\tau_{\text{bulk}}\sigma v_{\text{th}}N_{\text{ta}} p_{\text{n}} + 2[p_{\text{n}} + n_{\text{i}}\cosh\{(E_{\text{t}} - E_{\text{i}})/kT\}]}{\tau_{\text{bulk}}\sigma v_{\text{th}} N_{\text{tc}}p_{\text{n}} + 2[p_{\text{n}}+ n_{\text{i}}\cosh \{(E_{\text{t}} - E_{\text{i}})/kT\}]}. \end{equation} \tag{ 7 }$

At the deep level, Eq. (7) can be approximated as

$\begin{equation} \frac{\tau_{\text{c}}}{\tau_{\text{a}}} = \frac{\tau_{\text{bulk}}\sigma v_{\text{th}}N_{\text{ta}} + 2}{\tau_{\text{bulk}}\sigma v_{\text{th}}N_{\text{tc}} + 2}. \end{equation} \tag{ 8 }$

Equation (8) indicates that τ_c/τ_a is independent of the excess carrier density at the deep level. Figure 9 shows the relationship between τ_c/τ_a and the trap energy level, calculated from Eq. (7). With deep levels such as E_t − E_i = 0.0–0.2 eV, the same τ_c/τ_a is maintained at any excess carrier density. This is explained by Eq. (8). With shallow levels such as E_t − E_i = 0.3–0.4 eV, τ_c/τ_a varies greatly.

**Fig. 9.** Calculated relationship between trap energy level and carrier lifetime ratio (T = 300 K).
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In other words, at low- or medium-level excess carrier densities, τ_c/τ_a is larger with deep levels than with shallow levels. At high excess carrier densities, τ_c/τ_a is smaller with deep levels than with shallow levels.

3.3. Summary

From Figs. 5 and 9, it can be seen that the surge voltage is lower at deep levels in low and medium current regions, and at shallow levels in high current regions.

Figure 10 shows the simulated dependence of the surge voltage on the current at various trap energy levels. To obtain a high current density, the diode area was reduced from that considered in the previous simulations. At 1000 A/cm² or less, a low surge voltage is obtained with deep levels such as E_t − E_i = 0.0–0.2 eV. On the other hand, at a value greater than 1000 A/cm², the lowest surge voltage is obtained when E_t − E_i = 0.4 eV. This trend matches that shown in Figs. 5 and 9. Shallow levels suppress surge voltage only when there is a very high current. Thus, deep levels such as E_t − E_i = 0.0–0.2 eV are favorable for almost all power devices.

**Fig. 10.** Simulated dependence of recovery surge voltage with various trap energy levels (T = 300 K).
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The effect of surge reduction on power efficiency is not very large. However, the gate resistance of IGBT can be small because of surge reduction. Figure 11 shows the simulated relationship of the IGBT turn-on loss plus the diode recovery loss and trap energy levels at 550 A/cm². The gate resistance was adjusted to coincide with the surge voltage. The turn-on loss can be suppressed by decreasing the gate resistance. In the case where the surge voltage was maintained constant by adjusting the gate resistance, the energy loss decreased with deep levels.

**Fig. 11.** Simulated relationship between IGBT turn on loss plus diode recovery loss and trap energy levels at constant surge voltage by adjusting gate resistance (T = 300 K).
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Therefore, deep levels can suppress the surge voltage and energy loss. However, these deep levels produce high leak currents. In other words, there is a trade-off between the surge voltage and the leak current.

Figure 12 shows a pattern diagram of trap energy levels created by irradiating charged particles such as electrons, protons, and helium ions.³⁰^–³⁶⁾ This diagram shows that VV(—/0), VP, V₂H, and V₂O(—/0) satisfy the condition E_t − E_i < 0.2 eV. For surge voltage suppression, these irradiation techniques are effective. In addition, the effect of trap energy level can be controlled by adjusting the ratio of two trap concentrations. The trap energy level obtained from two trap energy levels serves as the intermediate level. In the case of charged particle irradiation techniques, the ratio of deep levels VV(—/0) to shallow levels VO(—/0) can be controlled using the annealing time, oxide concentration, and irradiation energy.³⁰^,³²⁾ Therefore, these techniques can also adjust the trade-off between the surge voltage and the leak current.

**Fig. 12.** Diagram of trap energy levels created by local lifetime control in silicon.
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4. Conclusions

The effects of the trap energy levels created by localizing traps at the anode side on surge voltage were investigated in silicon power diodes. It was found that deep trap energy levels suppress surge voltage when the current density is 1000 A/cm² or less, and that shallow trap energy levels reduce surge voltage when the current density is greater than 1000 A/cm².

Suppression of reverse recovery surge voltage of silicon power diode by adjusting trap energy levels through local lifetime control

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Abstract

1. Introduction

2. Methods

3. Results and discussion

3.1. Device simulation analysis: carrier lifetime profile dependence of reverse recovery surge voltage

3.2. Theoretical analysis: trap energy level dependence of carrier lifetime profile

3.3. Summary

4. Conclusions

Suppression of reverse recovery surge voltage of silicon power diode by adjusting trap energy levels through local lifetime control

Article metrics

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Share this article

Author e-mails

Author affiliations

Dates

Abstract

1. Introduction

2. Methods

3. Results and discussion

3.1. Device simulation analysis: carrier lifetime profile dependence of reverse recovery surge voltage

3.2. Theoretical analysis: trap energy level dependence of carrier lifetime profile

3.3. Summary

4. Conclusions