Silicon nanodisk array with a fin field-effect transistor for time-domain weighted sum calculation toward massively parallel spiking neural networks

A nanodisk array connected with a fin field-effect transistor is fabricated and analyzed for spiking neural network applications. This nanodevice performs weighted sums in the time domain using rising slopes of responses triggered by input spike pulses. The nanodisk arrays, which act as a resistance of several giga-ohms, are fabricated using a self-assembly bio-nano-template technique. Weighted sums are achieved with an energy dissipation on the order of 1 fJ, where the number of inputs can be more than one hundred. This amount of energy is several orders of magnitude lower than that of conventional digital processors.


F
or artificial intelligence, especially that realized by neural network models, a vast number of arithmetic calculations and memory that can change by learning mechanisms are two essential functions.To realize these functions at the device or material levels, various devices have recently been proposed.][7][8][9] In particular, the weighted summation, or multiplyand-accumulation, operation is an essential but computationally intensive task in these models.
In contrast to digital processors, analog operations of complementary metal-oxide-semiconductor (CMOS) circuits are promising for achieving extremely low power consumption operations of such computational tasks.Although calculation precision is limited because of deficient analog operations such as noise and device mismatches, neural network models and circuits can be designed to be robust to such non-idealities. 10)In contrast to the conventional weighted summation operation using analog voltages or currents, time-domain computations based on spiking neuron models lead to extremely low-power operations.
In this work, we propose a nanodevice that performs a time-domain weighted-sum operation.Experimentally, using a circuit with a nanodevice, we show that the weighted summation can be calculated in several microseconds with energy of approximately 1 fJ.
A simple spiking neuron model is shown in Fig. 1(a), which is known as an integrate-and-fire-type (IF) neuron model. 11)In this model, a neuron receives spike pulses via synapses.A spike pulse, which is simply called a spike, only indicates the input timing, and its pulse width and amplitude are arbitrary and do not affect subsequent processing.A spike generates a temporal voltage change, which is called a post-synaptic potential (PSP), and the internal potential of the n-th neuron, V n (t), is equal to the spatiotemporal summation of all PSPs.When V n (t) reaches the firing threshold θ, the neuron outputs a spike, and then V n (t) settles back to the steady state.Refractory period and leaky mechanisms are usually added in this model.
Based on the model proposed by Maass,11) a simplified weighted-sum operation model using IF neurons is proposed.
Arbitrary time span T in , during which only one spike is fed from each neuron, is defined.Here, it is assumed that a PSP generated by a spike from neuron i increases linearly with slope k i from the timing of the spike input, t i , as shown in Fig. 1(a).The required weighted sum operation is defined as follows: a normalized variable x i (0 ≤ x i ≤ 1) is multiplied by a predefined normalized weight coefficient a i (−1 < a i < 1), and the multiplication results are summed over all i (i ¼ 1; 2; . . .; N), where N is the number of inputs; furthermore, there is the constraint that P N i¼1 a i ¼ 1.This weighted sum operation can be performed using the rise timing of PSPs in the IF neuron model.We assume that spikes are input at time t i , each of which represent x i , where Coefficients a i are transformed into the PSPs' slopes k i ; k i = λa i , where λ is an arbitrary transformation constant.If the firing time of the neuron is defined as t ν , the following equation is easily obtained: If time span T out is defined as θ=λ, after several transformations, the weighted sum of the inputs can be expressed by the output spike timing t ν : Thus, if time t ν is measured, the weighted-sum result is obtained by calculating the right-hand side of Eq. ( 2).
Note that the number of freely determined weights is not N, but N − 1.For example, if N = 2, a i or k i are dependent on each other.
The aforementioned calculation model can approximately be implemented using a circuit that consists of a field-effect transistor (FET) connected with an array of resistors, as shown in Fig. 1(b).An approximate linear slope k is generated by capacitance C of the FET gate and resistance R with step voltage input V in .In the time-domain calculation, the time constant related to processing should be fairly long, such as 1 µs, to guarantee a high calculation resolution.If C is assumed to be 1 fF, which is a typical value for the gate capacitance of a nanoscale MOSFET, R should be on the order of 1 GΩ for a time constant of 1 µs.Such high resistance is difficult to obtain without a large variation in current silicon very large scale integration (VLSI) technology.
Under the above assumption, the energy consumed for a weighted-sum operation, E ws , is CV 2 , where V is the operation voltage; therefore, E ws = 1 fJ for V = 1 V. Furthermore, if N resistors are connected with capacitor C for N-parallel multiplication operations, the energy required for one multiplication operation, E m , is E ws =N, i.e., E m = 1 aJ for N = 1,000, which is more than several orders of magnitude smaller than current highest efficiency digital processors. 12)s a device that performs the aforementioned time-domain operation, we propose a nanodisk array (NDA) structure on a MOSFET. 13)The NDA structure generates PSPs by taking advantage of the delay in electron hopping movement among nanodisks.Such an NDA structure can be fabricated using a bio-nano template process, which combines the self-assembly property of ferritin supramolecules and a neutral beam etching technique. 14)Ferritin is a supramolecule that has an iron core inside of a protein shell.A real NDA structure was fabricated on a planar substrate, and the PSP generation operation was successfully verified. 15)In this work, NDAs are fabricated and directly connected on the gate of an n-type fin FET (FinFET).The schematic views and dimensions of the major parts of the proposed device are shown in Fig. 2. The gate capacitance of the FinFET is approximately 230 aF, and such small capacitance leads to an extremely low power consumption operation, as described above.
The proposed nanodevice was fabricated as follows.First, FinFETs were fabricated on an SOI wafer using the established technology, 16) silicon dioxide films were depos-ited on the FinFETs, and their surfaces were planarized by a chemical mechanical polishing (CMP) technique.The CMP process must be stopped when the gate electrodes of FinFETs are exposed.To this end, dummy patterns for end-point detection in the CMP process were arranged around a FinFET.A microphotograph of the plan view observed after planarization by CMP is shown in Fig. 3(a).Transmission electron microscopy (TEM) micrograph of the cross-sectional view of a FinFET gate, where the top surface is planarized with a silicon dioxide film, is shown in Fig. 3

(b).
A polysilicon film was formed on the planarized silicon dioxide surface, which was spin-coated with a solution including ferritin supramolecules, and a self-assembled ferritin array was formed on the film.After removing the protein shells by heat treatment, a regular arrangement of iron cores remained on the film.Using this iron core array as  an etching mask, the polysilicon film was etched with defect-free neutral beams. 14,15)As a result, an array of polysilicon nanodisks was formed, and each nanodisk had approximately the same diameter and between nanodisks as the iron core.Scanning electron microscopy (SEM) micrographs of a ferritin supramolecule array are shown in Figs.3(c) and 3(d).The diameter and thickness of the fabricated nanodisks were 10 and 4 nm, respectively, and the space between the nanodisks was 3 nm.In this work, NDAs were used as formed without a patterning process.Multiple input electrodes were arranged near the gate of the FinFET with contact holes to connect with an NDA, as shown in Fig. 2

(b).
To evaluate the electrical characteristics of NDAs, we designed and fabricated test devices, each of which consisted of an NDA uniformly formed on a wafer and aluminum electrodes connected with an NDA via contact holes.The resistance was measured using a Keithley 2636 system sourcemeter with different distances between the two contact holes.The resistance of NDAs was compared with those of devices without NDAs with and without CMP as a control.Only devices with both CMP and NDA were fabricated on a planarized silicon oxide film area formed after the FinFET fabrication process.The others were fabricated on a planar silicon oxide film formed on a bare wafer.
The measurement results are shown in Fig. 4, where the applied voltage is 10 V. Currents on the order of 0.1 nA flow in the devices with both CMP and NDA, while nearly no currents flow in the devices without NDA.The resistance of NDA was on the order of 10 GΩ, roughly inversely proportional to the distance between the contact holes, which corresponds to the number of nanodisks contributing to electron hopping.
We set up a measurement system for evaluating a timedomain weighted-sum operation, as shown in Fig. 5(a).We constructed n-type MOS inverter circuits to detect the gate voltage change resulting from the currents generated by input pulses via an NDA.Because the driving ability of a single FinFET is small, a second-stage inverter that consisted of a FinFET and external resistor R L was used.The output of the inverter was detected by an active probe (Tektronix P6243) of a digital oscilloscope (Tektronix TDS5104B).The input pulses represent negative logic, and the observed output voltage V out also decreases when input pulses are given, as shown in Fig. 5(b).Here, the three inputs maintained their voltages from their spike timing, which corresponds to V in shown in Fig. 1(c).After the weighted-sum calculation was completed, the inputs were settled back to their original voltages, and the output voltages were also settled to their original voltages.
In this circuit, an NDA acts as a high resistance element with approximately 10 GΩ.The NDA and the gate capacitance of the FinFET form a resistance-capacitance circuit with a time constant of approximately 1 µs.From the beginning of fall timing of the responses generated by input spike pulses, the output voltage decreases approximately linearly with a slope proportional to input pulse voltage V in , which corresponds to k i in Eq. ( 1).We measured the timing when V n (t) exceeded the threshold θ as t ν .Parameters T in and T out were set to 10 and 1.17 µs, respectively, which can be set arbitrarily as previously described, and weighted sums were calculated using Eq.(2).
Figure 5(c) shows the result for a three-input case, where input x 3 , corresponding to input timing t 3 , and normalized slope a 3 are varied.Note that due to the constraint about the sum of a i , a 3 is varied by changing a 1 and a 2 .Here, the voltages of V in1 , V in2 , and V in3 , which determine a i , are changed as shown in Fig. 5(c).Because of the nonlinearity of the resistance-capacitance circuit shown in Fig. 1(c), relatively large errors occur in some cases.However, these errors are expected to decrease as the number of inputs increases.Figure 5(d) shows the relationship between the left-hand and right-hand sides of Eq. ( 2).We verified from these measurement results that the time-domain weightedsum operation is successfully achieved with an average error of less than 3% even if some cases show large errors.
In conclusion, NDA structures with a FinFET were fabricated using conventional silicon VLSI technology selfassembly bio-nano-template techniques.Using the device, a time-domain weighted-sum operation based on spiking neural networks was verified and analyzed.To realize a resistance-capacitance circuit for the time domain operation, the NDA was used as a resistor of the order of 10 GΩ, and the gate of a FinFET acted as a capacitor of approximately 200 aF.By measuring three-input nanodisks with a FinFET, we verified that the weighted-sum operation is achieved with an error of less than 3%.The energy required for a weighted sum was approximately equal to 1 fJ, which is several orders of magnitude lower than that of conventional digital processors.The proposed device has no learning mechanism, but combining a memristor device with the proposed device is a promising solution.Therefore, the proposed device is adventageous for constructing massively parallel neural network hardware with extremely low power consumption.

Fig. 1 .
Fig. 1.IF neuron model for the weighted-sum operation: (a) schematic of the model and weighted-sum operation using rise timing of PSPs; (b) circuit diagram in which resistors are connected with the gate of an FET for the weighted sum operation, where each resistor is equipped with a rectification function to prevent an inverse current; (c) time courses in a resistancecapacitance circuit.

Fig. 2 .
Fig. 2. Schematic views of the proposed device that consists of an n-type FinFET and NDAs with two input electrodes: (a) bird's-eye view and (b) plan view.Although NDAs are drawn as formed within restricted areas, they are actually formed uniformly on the wafer surface.The FinFET gate and two contact holes connecting an NDA and electrodes are shown.For four-input test devices, two contact holes and electrodes are formed at each side.

Fig. 3 .
Fig. 3. Micrographs of NDAs with a FinFET structure: (a) microphotograph of a test device after planarization, where a FinFET is located at the center, and square patterns around that are dummies for end-point detection in CMP; (b) TEM micrograph of a cross-sectional view of a FinFET gate, where the top surface is planarized; (c) SEM micrograph after a spin-coated process of ferritin solution on the planarized surface; (d) SEM micrograph of a ferritin self-assembled array arranged on the planarized surface, where the inset is an enlarged image.

Fig. 4 .Fig. 5 .
Fig. 4. Current measurement results as a function of the distance between contact holes.