GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

F or future efficient and low-cost power electronics, GaN high-electron-mobility transistors (HEMTs) on silicon (Si) substrate are highly promising owing to their superior intrinsic properties such as large bandgap, high breakdown field strength, and high electron saturation velocity. [1][2][3][4][5][6][7][8][9] However, GaN-on-Si transistors suffer from poor critical electrical field strength of the Si substrate together with a parasitic conduction at the buffer=substrate interface leading to device breakdown. [10][11][12] Therefore, the highest reported three-terminal breakdown voltage (V BD ) values for GaN-on-Si HEMTs defined at an off-state leakage current of 1 µA=mm are still below 1.5 kV, 13) which is basically limited by the Si substrate and the associated material quality. [14][15][16][17][18][19][20][21] To suppress the parasitic conduction phenomenon, a local Si substrate removal (LSR) was proposed in 2010. 22,23) The Si substrate removal around the drain electrode enabled the electrical isolation of the gate and source from the drain across the buffer layer=Si interface, leading to an enhanced blocking voltage of the GaN-on-Si HEMT above 2 kV. 24) Using this approach, our group reported GaN-based transistors with a significantly improved blocking voltage of 3 kV, 25) but still with a high leakage current that is not compatible with high-power applications.
In this paper, we report for the first time GaN-on-Si metalinsulator-semiconductor HEMTs (MISHEMTs) with LSR under the entire device followed by a backside deposition of the ultra-wide bandgap AlN material. The use of an in situ SiN gate dielectric under the gate and the LSR technique combined with 15-µm-thick AlN layer enabled the state-ofthe-art GaN-based HEMTs with remarkably low off-state leakage current (<1 µA=mm) up to 3 kV.
The AlGaN=GaN=AlGaN double heterostructures were grown using metalorganic chemical vapor deposition (MOCVD) on a 6-in. Si(111) substrate. The HEMT structure consists of an AlN nucleation layer followed by AlGaNgraded transition layers and an Al 0.08 Ga 0.92 N buffer layer. The 5 µm total buffer thickness was followed by a 150-nm GaN channel, a 20-nm Al 0.25 Ga 0.75 N barrier layer and a 50-nm in situ Si 3 N 4 cap layer [ Fig. 1(a)]. Hall effect measurements revealed an electron sheet concentration of 8.9 × 10 12 cm −2 with a mobility of 2190 cm 2 ·V −1 ·s −1 and a sheet resistance R SH = 319 Ω=□ at room temperature with a high uniformity of less than 4% across the wafer. Ohmic contacts were formed directly on top of the AlGaN barrier by alloying the Ti=Al= Ni=Au stack at 875°C using rapid thermal annealing. Device isolation was achieved by N 2 implantation. The metal-insulator-semiconductor (MIS) gate structure was employed by depositing the Ni=Au metal stack on the in situ Si 3 N 4 cap layer (30-nm-thick SiN left under the gate) without any additional field plate. A 200-nm-thick SiN film was deposited using plasma-enhanced chemical vapor deposition (PECVD) as extra passivation. Once the front-side processing was completed, the Si substrate was locally etched up to the AlN nucleation layer around the entire device (50 µm away from the sidewalls), as shown in Fig. 1(b). It is noteworthy that our mask design consists of devices with and without LSR patterns, which eliminates any processing or epi variations during the device characterization [ Fig. 2(a)]. Figure 2(b) depicts a backside view of a crack-free 20 × 500 µm 2 GaNbased MISHEMT after the LSR technique.
Subsequently, a 15-µm-thick AlN was deposited on the backside by physical vapor deposition (PVD) at 300°C by Kyma Technologies. Figure 3 breakdown voltage characteristics, several thicknesses have been deposited on a highly doped Si. The PVD AlN film delivered a high breakdown field above 4 MV=cm despite the low temperature deposition, and offers a cost-effective manufacturing technology scalable up to 8 inches, considering that the LSR approach is also applicable in large-diameter wafers. In addition, Fig. 3 Electrical characterizations were carried out on devices with gate width=length = 50 µm=2 µm and a gate-to-drain spacing (L GD ) that varied from 2 to 40 µm with and without LSR= backside AlN and Cu deposition on the same wafer. The DC transfer and I D -V D characteristics of the AlGaN=GaN MISHEMTs with an L GD of 40 µm are shown in Fig. 4. The maximum current density at V GS = +1 V decreased by approximately 30% from 8.8 to 6.3 mA=mm after the Si substrate removal under the active region due to self-heating. The origin of the self-heating subsequent to substrate removal is the degradation of the thermal dissipation in air, resulting in an increase in the channel temperature, which decreases the electron mobility and thus causes a reduction in the drain current. Indeed, the devices with LSR have been recently reported to have lower thermal conductivities than those without LSR by the Raman thermometry technique. 26) However, a significant recovery of the maximum current density (approximately 85%), with respect to the devices without LSR, occurs after the highly thermally conductive Cu deposition, which in turn enables the strong reduction in self-heating [ Fig. 4(b)]. The static specific on-resistance (R ON-STATIC ) values were extracted to be 13.1 and 13.2 mΩ=cm 2 for devices with L GD = 40 µm, without and with LSR=thick AlN and Cu, respectively. The active area of the devices with L GD = 40 µm was calculated to be 2.6 × 10 −5 cm 2 by considering a 5 µm transfer length for each ohmic contact (i.e., source and drain).    Three-terminal V BD measurements were conducted on various transistor designs from 2 to 40 µm at V GS = −8 V with a floating substrate using a Fluorinert solution. V BD was defined as the drain-source voltage (V DS ) at which the drain current density (I D ) reaches 1 µA=mm. The specific on-resistances and breakdown voltages without and with LSR=thick AlN and Cu for each design are represented in Fig. 5(a). For devices without LSR, V BD saturated at approximately 600 V for L GD larger than 10 µm resulting from the parasitic substrate conduction between the metal contacts and the Si substrate, regardless of the device geometry. The device breakdown occurs at the AlN=Si interface because of the lower breakdown field of Si compared to the III-nitride layers (E AlN = 11.7 MV=cm and E Si = 0.3 MV=cm). 10,11) On the other hand, for devices with LSR=thick AlN and Cu, the substrate leakage contribution is suppressed and V BD further increased with the gate-to-drain distance while still delivering low specific on-resistances.
The three-terminal off-state leakage characteristics of the AlGaN=GaN MISHEMTs with and without LSR=thick AlN and Cu are plotted as a function of V DS for the largest design, i.e., L GD = 40 µm in Fig. 5(b). The devices without LSR demonstrated an exponential increase in the leakage current at low V DS bias reaching the 1 µA=mm limit at approximately 600 V owing to the parasitic conduction through the buffer=Si substrate. For devices with LSR=thick AlN and Cu, the drain leakage current density was reduced by approximately two orders of magnitude from 600 V to 3 kV, confirming the suppression of the substrate's conductive-path contribution. It is noteworthy that the off-state gate leakage (I G ) currents of both AlGaN=GaN MISHEMT designs, with and without LSR are below 1 µA=mm until the device breaks down owing to the gate dielectric under the gate. Therefore, despite common perception, the drain leakage current flowing through the buffer layers is not especially due to the bulk defects=traps but is more confined at the AlN nucleation layer=Si substrate interface. Figure 6 shows a benchmark of the GaN-on-Si HEMTs blocking voltage defined at an off-state leakage current of 1 µA=mm. [27][28][29][30] The translated specific R ON of 13 mΩ·cm 2 combined with a blocking breakdown voltage of 3 kV, for devices with L GD = 40 µm sets the state-of-the-art device. These results pave the way for higher-voltage-operation GaN-on-Si power devices.
We demonstrated for the first time GaN-on-Si MISHEMTs with local Si substrate removal under the entire device followed by a low-cost backside deposition of a thick ultrawide bandgap AlN film. Using an MIS gate structure and the LSR technique combined with a 15-µm-thick AlN layer resulted in state-of-the-art GaN-based HEMTs with remarkably low off-state leakage current (<1 µA=mm) beyond 3 kV. The comparison of these devices without LSR proves that the drain leakage current flows at the AlN nucleation layer=Si substrate interface. Furthermore, the significant recovery of the maximum current density after the backside Cu deposition enabled the reduction in self-heating. This work shows that this emerging type of devices could be useful for cost-effective applications requiring breakdown voltages above 3 kV.