Thin channel β-Ga2O3 MOSFETs with self-aligned refractory metal gates

We report the first demonstration of self-aligned gate (SAG) β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) as a path toward eliminating source access resistance for low-loss power applications. The SAG process is implemented with a subtractively defined and etched refractory metal, such as Tungsten, combined with ion-implantation. We report experimental and modeled DC performance of a representative SAG device that achieved a maximum transconductance of 35 mS mm−1 and an on-resistance of ∼30 Ω mm with a 2.5 μm gate length. These results highlight the advantage of implant technology for SAG β-Ga2O3 MOSFETs enabling future power switching and RF devices with low parasitic resistance.

I nterest in beta-phase Gallium Oxide (β-Ga 2 O 3 ) as a nextgeneration ultra-wide bandgap semiconductor is due to its potential for use in high efficiency power applications. β-Ga 2 O 3 possesses a bandgap of ∼4.8 eV with an estimated critical field strength (E c ) of ∼8 MV cm −1 which is 2-3× higher than GaN and SiC. 1,2) Power switching conduction losses, defined by Baliga's figure of Merit, 3) are a cubic function of E c , and empirical E c values for β-Ga 2 O 3 have already surpassed the theoretical limits for GaN and SiC. 4) β-Ga 2 O 3 metal-oxide-semiconductor field-effect transistors (MOSFETs) have demonstrated the ability to block high voltages near and surpassing 1 kV in depletion [5][6][7][8][9] and enhancement 10,11) mode operation. For β-Ga 2 O 3 RF devices, the Johnson's figure of Merit 12) compares favorably to GaN as reports of modeled saturation velocity reach as high as ∼2 × 10 7 cm s −1 . 13) Low-GHz β-Ga 2 O 3 RF power devices have been reported 14) as well as high frequency small signal results with T-gates. 15,16) Most early device results, however, suffer heavily from resistive parasitic losses both in the drift (R drift ) and source access (R S ) regions. The R S is a critical device parameter that limits device transconductance (G M ) expressed as: G M,ext is the extrinsic G M measured in saturation with parasitic losses and G M,int is the intrinsic value. Removal of parasitic resistance such as access resistance (R S,access ) is imperative for lateral device scaling due to β-Ga 2 O 3 's low mobility relative to other materials. For example, the sheet resistance of GaN HEMTs are typically at least an order of magnitude lower than previously reported β-Ga 2 O 3 channels. β-Ga 2 O 3 is amenable to Si ion-implant; therefore, it is the only semiconductor material with a band gap larger than SiC that can be designed with a self-aligned gate (SAG) process. A SAG process was previously reported for β-Ga 2 O 3 that eliminated R S,access with better DC performance compared to non-SAG devices. 17) Here, we expand on the SAG process, device characterization and benchmark the results. The measured G M,ext and I DS is among the highest measured for Ga 2 O 3 MOSFETs. A Sentaurus TCAD device simulation is included to support the measured data and predict performance with deep sub-micron gate length scaling.
The device sample was prepared with a single 22 nm thick Si-doped β-Ga 2 O 3 homoepitaxial channel layer grown by metal organic vapor phase epitaxy directly on a semiinsulating (010) Fe-doped substrate at Leibniz-Institut für Kristallzüchtung -Berlin, Germany. 18) The device fabrication process began by depositing ∼30 nm of Al 2 O 3 by plasmaenhanced atomic layer deposition to serve as the gate dielectric as well as an implant cap. Next, a W refractory metal layer was sputtered and patterned with a Cr hard mask to subtractively define a 2.5 μm W/Cr gate electrode with SF 6 reactive ion etch (RIE) chemistry. A refractory metal gate is vital to a self-aligned process because an Au-based gate metal stack would not remain intact at the required implant activation temperature. Si-implant regions were then patterned with the source-side of the W/Cr gate exposed to eliminate the gate-source region (L GS = 0 μm), while the gate-drain distance (L GD ) remained, measuring 0.25 μm. A shallow Si-implant profile was designed with 10 and 35 keV energies with a total dose of 1 × 10 15 ions cm −2 to achieve a target 1 × 10 20 cm −3 doping concentration. The Si-implant was activated at 900°C for 120 s using rapid thermal annealing (RTA) in a N 2 ambient. Ohmic contact to the implanted regions was achieved with a Ti/Al/Ni/Au evaporated metal stack followed by a 470°C RTA process for 1 min in a N 2 ambient after removing the implant cap with RIE. Electrical isolation was achieved with inductively coupled plasma/reactive ion etching. Finally, additional Ti/Au gate and interconnect metal was added for device characterization.
Displayed in Fig. 1(a) is a schematic of a representative β-Ga 2 O 3 SAG MOSFET. The source-drain distance (L SD ) between the implanted regions is ∼2.75 μm and the gate length (L G ) is ∼2.5 μm. Van der Pauw test structures were measured after fabrication to track sheet charge density (n sh ), sheet resistance (R sh ) and mobility (μ) with average values of n sh = 4.96 × 10 12 cm −2 , R sh = 2.6 × 10 4 Ω sq −1 , and μ = 48.4 cm 2 V −1 s −1 , respectively. The R sh and R C of the implanted regions are on the order of 2.0 × 10 3 Ω sq −1 and 1.5 Ω mm respectively based on measurements from samples with a similar doping profile.
A scanning electron microscope image of the 2 × 50 SAG MOSFET is shown in Fig. 1(b). High-resolution transmission electron microscopy (HR-TEM) inspection images of the SAG MOSFET were prepared in the regions under the gate and on the source-side of the gate with Si ion-implantation [see Figs. 1(c)-1(e)]. Lattice planes of (010) β-Ga 2 O 3 are visible in the implanted region showing no structural defect following the implant activation anneal. Similarly, the gate dielectric appears preserved after 900°C implant activation with no indication of polycrystalline domains, and the W gate electrode maintains a sharp interface with the gate dielectric layer.
The DC I-V characteristics of the SAG MOSFET are shown in Figs. 2(a)-2(c). The transfer curve is shown in Fig. 2(a)   was extracted from the log I DS -V GS curve in Fig. 2(b) which is indicative of the strong channel control expected from a large L G and ultra-thin MOSFET channel. Additionally, no adverse effects of implant activation on gate leakage were observed at −10 V gate bias [see Fig. 2(b)]. The output family of curves is displayed in Fig. 2(c) obtained over a range of V GS from +4 to −2 V including an on-resistance (R ON ) of 30 Ω mm at V GS = 4 V calculated from a linear fit at small V DS . The R ON near the ideal flat-band voltage (V G = 0) was calculated with a series resistance model based on the sum of contact resistance (R C ), access resistance (R access ), channel resistance (R channel ), and drift region (R drift ) to be ∼73 Ω mm which is in good agreement with ∼70 Ω mm extracted from the model and measurement in Fig. 2(c).
The modeled results in Figs. 2(a)-2(c) (solid lines) were constructed by solving the drift-diffusion electron transport equation in ISE Sentaurus Device of the same SAG MOSFET. The model uses dimensions extracted from TEM measurements, as well as material properties (n sh , μ, R sh ) from the measured device or nearest test structure. The Al 2 O 3 thickness was also extracted from the HR-TEM image, and the dielectric constant was assumed to be 9.6. The model is in excellent agreement with the measured results with only some deviation at forward gate bias. The discrepancy is likely due to ideal assumptions concerning electron accumulation, channel doping uniformity, and trapping effects. Thermal effects were not considered but are expected to have an impact at higher V DS and V G bias and especially for an aggressively scaled device (e.g. where dissipated power is greater). Modeling of the same device with L G = 0.5 μm is included (gray) here to observe the benefits of L G scaling under the assumption that temperature will be effectively managed, such as by pulsed operation. With a reduced gate length, a significant improvement in G M , I DS , and R ON to 60 mS mm −1 , 350 mA mm −1 and 17 Ω mm respectively, is expected. This illustrates the potential for future highperformance Ga 2 O 3 devices with deep sub-micron gate length and vertically scaled epitaxial device designs.
Benchmarking of these results in Fig. 3 shows a plot of G M versus L G for SAG β-Ga 2 O 3 MOSFETs in this work compared to β-Ga 2 O 3 devices reported in the literature. [19][20][21][22][23] With the exception of vertically scaled delta-doped β-Ga 2 O 3 MESFETs, the G M results are state-of-the-art and achieved with a large gate length. Significant improvements are expected with deep sub-micron gate length scaling following the G M,ext ≈ v ext ·C GS /L G relationship where v ext and C GS are extrinsic electron velocity and gate-source capacitance, respectively. Further reduction in access resistance can occur by optimizing implant sheet and contact resistance. For example, in our reported MOSFET, the implant R SH accounts for approximately 15% of the total device resistance.
We have presented the first SAG β-Ga 2 O 3 MOSFET using a refractory metal gate-first design with Si ion-implantation. The SAG process eliminates source access resistance with among the highest G M values reported for β-Ga 2 O 3 MOSFETs. The data was compared with a physics-based device simulation which shows strong agreement with the measured results. Additionally, the potential of this process was shown via a device model with gate scaling applied. The SAG process will be essential for future β-Ga 2 O 3 device engineering to achieve high-performance, ultra-low power loss devices.