Operation of thin-film thermoelectric generator of Ge-rich poly-Ge1-xSnx on SiO2 fabricated by a low thermal budget process

A thin-film thermoelectric generator composed of p- and n-type poly-Ge1−xSnx (x ∼ 0.02) on a Si(001) covered with SiO2 has been successfully fabricated by low thermal budget processes (under 300 °C) and demonstrated for the first time. Both the crystallization and dopant activation were simultaneously performed using pulsed UV laser irradiation in flowing water. A recorded activation ratio of Sb in the poly-Ge1−xSnx enabled a relatively high power factor (9.2 μ Wcm−1 K−2 at RT), which is comparable to the counterparts of n-type Ge1−xSnx layers epitaxially grown on InP(001).

S equential 3D integration of a thin-film energy-harvesting device in a silicon (Si) chip [1][2][3][4][5][6] is strongly desired for realizing a standalone sensing network system, called the internet-of-things society and/or trillion sensor universe, coupled with low-power consumption technologies. The thermoelectric generator (TEG), which could convert waste heat into electricity, is one of the options. Taking the distribution of a huge number of sensors all over the world into consideration, the utilization of the same technology to manufacture next-generation Si-based integrated circuits (ICs) is preferable, including the material. In addition, from a physics viewpoint, a small amount of tin (Sn)-incorporated germanium (Ge), which is called Ge-rich Ge 1−x Sn x in this letter, is one of the attractive TEG materials owing to its higher carrier mobility, 7,8) lower thermal conductivity 9,10) and lower polycrystallization temperature 11,12) than those of Si and Si 1−x Ge x .
Against such a background, we recently developed a new method to perform dopant activation and polycrystallization simultaneously by using pulsed UV laser annealing (duration: 55 ns, wavelength: 248 nm) through flowing water, for antimony (Sb)-doped amorphous Ge 1−x Sn x (a-Ge 1−x Sn x ) layers with an initial Sn content of 2%. 38) Thanks to the extremely short penetration depth of the UV laser and cooling effect by the water, the process temperature in the underlying Si substrate covered with a 1-μm-thick SiO 2 could be maintained at less than 50°C. 39) In addition, it was revealed that the ultra-short-time annealing was effective to suppress a significant segregation of Sb atoms, and thus, a high activation ratio of Sb (64%) could be obtained, resulting in a heavy n-type doping over 10 20 cm −3 . It is noted that the obtained activation ratio (64%) is at least five times larger than previous experimental results in Ref. 40, where an activation ratio of 13% was obtained for a phosphorus (P)doped poly-Ge layer with an initial P content of 1 × 10 20 cm −3 crystallized by FLA. In this letter, we first present the thermoelectric properties of the n-type poly-Ge 1−x Sn x layers grown on SiO 2 for realizing poly-Ge 1−x Sn x thin-film TEGs. 3D integration and operation of the thin-film TEG composed of p-and n-type poly-Ge 1−x Sn x (x ∼ 0.02) on a Si chip have been successfully demonstrated for the first time using low thermal budget processes under 300°C.
An n-type Si(001) wafer covered with a 1-μm-thick SiO 2 layer was used as the substrate; the thickness of the a-Ge 0.98 Sn 0.02 layers with a dopant on the substrates was fixed as 50 nm. The a-Ge 0.98 Sn 0.02 layers were deposited at RT using a molecular beam deposition (MBD) method with a solid source at a deposition rate of ∼0.04 nm s −1 . The element for the n-or p-type doping was chosen as Sb or gallium (Ga), respectively, which have oxidation resistance during the pulsed laser annealing (PLA) in flowing water as discussed in the previous works; 38,39) the dopant concentration of Sb (Ga) was 1−6 × 10 20 (3 × 10 20 ) cm −3 . To obtain a large grained growth, high-power (E = 250-270 mJ cm −2 ) laser irradiation was performed on the a-Ge 0.98 Sn 0.02 surfaces with a scan speed to correspond to 20-irradiation-times per location. As described above, the maximum temperature of the Si wafer could be maintained below 50°C and the temperature in all regions drops to 40°C only 10 μs after laser irradiation. 39) By using such a low thermal budget process, we fabricated poly-Ge 1−x Sn x -based thin-film TEGs. The key fabrication steps are summarized in Fig. 1(a). An a-Ge 0.98 Sn 0.02 layer with an Sb dopant of 1 × 10 20 cm −3 was deposited on the substrates using MBD. After deposition of a hard mask (HM) of a 200-nm-thick SiO 2 by plasma enhanced CVD (PECVD) at 300°C, the stack layers were patterned by wet etching to form island areas (length: 5 mm, width: 0.7 mm). Similarly, islands consisting of an a-Ge 0.98 Sn 0.02 layer with a Ga dopant of 3 × 10 20 cm −3 were formed between two islands of the Sbdoped Ge 0.98 Sn 0.02 layers. These a-Ge 0.98 Sn 0.02 layers were covered with the HM again and then crystallized using the PLA in water at E = 250 mJ cm −2 . After removing the HM, Al electrodes were formed at the end of the islands using thermal evaporation and a wet etching process to seriesconnect the n-and p-type islands alternately. The connected number of n-and p-type poly-Ge 1−x Sn x islands were two and three, respectively. Note that the maximum substrate temperature (300°C) was limited by the PECVD process, not the crystallization process by the PLA in flowing water.
For the thermoelectric measurements, two Peltier devices were placed under the substrate, as shown schematically in Fig. 1(b); they produced a thermal gradient −∇T from the heating to cooling region. Two sheathed thermocouples [TC1 and TC2 in Fig. 1(b)] were mechanically contacted at the first and final Al electrodes of the thin-film TEGs to monitor the temperature difference ΔT, voltage V, and current I simultaneously, where a semiconductor device analyzer (Keysight B1500A) was used to measure these parameters. The Seebeck coefficient S of the poly-Ge 1−x Sn x layers was determined from the slope of ΔT−ΔV plots before the island patterning; the carrier density and electrical conductivity σ were determined by Hall effect measurements using a micro-Hall-bar structure (length: 7 μm, width: 5 μm).
First, let us discuss the basic thermoelectric properties of σ and S measured at RT, as a function of the Hall electron density. They are summarized in Figs. 2(a) and 2(b), respectively. Experimental data for the Sb-doped poly-Ge 1−x Sn x layers (star symbols) and Sb-doped Ge 1−x Sn x layers with various Sn content (0%−14%) epitaxially grown on InP(001) (triangle symbols) 41) are plotted, where the gray-scale intensity in the triangle symbols corresponds to x. In Fig. 2(a), the Irvin curve for n-type bulk Ge (solid line) 42) is also plotted. The σ increases with the electron density and reaches the Irvin curve multiplied by 0.6 (dashed line) over the density of 5 × 10 19 cm −3 , which is owing to improvement of the mobility. In Fig. 2(b), we also    show S values of n-type Ge for comparison, which are theoretically calculated by solving the following Boltzmann transport equation 43) : where e is the elementary charge, T is the absolute temperature, E is the electron energy, E F is the Fermi energy, f is the Fermi-Dirac distribution function, g is the density of states and t is the relaxation time, which can be expressed by 1 1 j j t t = S / / and the j t is proportional to E 1.5 or E −0.5 depending on the scattering processes. Specifically, in a heavily doped region for polycrystals, there are three dominant scattering processes: ionized impurity scattering E , and grain boundary scattering E . implying that the short-range defect scattering and/or grain boundary scattering are still dominant even in the region of a relatively high electron density over 10 19 cm −3 . The trend is similar to the n-type Ge 1−x Sn x layers epitaxially grown on InP(001). 41) To clarify the PFs and compare them with other n-type TEG materials, we replot the values of σ and |S| for the poly-Ge 1−x Sn x layers in a logarithmic graph. They are summarized in Fig. 3, where epitaxial Ge 1−x Sn x layers, 41) bulk Si 1−x Ge x 47) and poly-Bi 2 (TeSe) 3 layer 48) are also shown for comparison. By tuning the σ and S in the electron density, a relatively high PF S 2 s = ( ) of 9.2 μ Wcm −1 K −1 was obtained for the poly-Ge 1−x Sn x layer. The maximum value is comparable to the counterparts of n-type Ge 1−x Sn x layers epitaxially grown on InP(001) (10 μ Wcm −1 K −2 ); 41) however, the obtained maximum value in the present study is still 38% of that for n-type poly-Bi 2 (TeSe) 3 layers (24 μ Wcm −1 K −2 ). 48) Note that σ in the poly-Ge 1−x Sn x is at least twice as low as the expected values from the Sbdoped Ge 1−x Sn x layers pseudomorphically grown on Ge(001). 49) Therefore, the present study does not indicate the limitation of n-type Ge 1−x Sn x . Here, for reference, we estimated values of the thermal conductivity κ of 3.0 Wm −1 K −1 at RT and the dimensionless figure of merit (zT = S 2 σT/κ) of ∼0.09 at RT for the poly-Ge 1−x Sn x layer with an initial Sb content of 2 × 10 20 cm −3 , although the measurement direction of κ (perpendicular to the substrate) is different to that of PF (parallel to the substrate). The measurements of κ were carried out by using the pico-second thermoreflectances in the front-detection-front-heating configuration (PicoTherm Corp. PicoTR). 50) The κ value (3.0 Wm −1 K −1 ) is approximately 20 times lower than that for bulk Ge (60 Wm −1 K −1 ) 51) and still lower than that for bulk Si 1−x Ge x (4.5 Wm −1 K −1 ); 47) consequently, the zT value (∼0.09 at RT) comparable to that for the bulk Si 1−x Ge x (∼0.1 at RT) 47) was achieved, although σ in the poly-Ge 1−x Sn x layer was degraded compared with bulk Ge.
By interconnecting the n-and p-type poly-Ge 1−x Sn x layers with Al electrodes, a thermoelectric operation was successfully observed, which is the first demonstration of poly-Ge 1−x Sn x thin-film TEGs with the in-plane π-type structure (Fig. 4). We confirmed a reasonable open-circuit voltage of 4.5 mV at ΔT = 10 K, which is almost consistent with the estimated value (5.3 mV) from S in the poly-Ge 1−x Sn x layers (n-type: −126 μV K −1 , p-type: 93 μV K −1 ). The obtained short-circuit currents, however, were at least three times smaller than the value expected from σ in the poly-Ge 1−x Sn x layers (n-type: 119 Scm −1 , p-type: 223 S cm −1 ), which is caused mainly by a large contact resistance at the interface between the Al and the n-type poly-Ge 1−x Sn x layers. This issue will be solved by using the Fermi-level depinning technique, which has been actively discussed in the field of metal contact with Ge. [52][53][54][55][56][57][58][59] Note that the maximum thermoelectric power (40 pW) obtained in the present study has not been optimized, so that the performance could be improved by tuning the carrier densities and reducing the internal and parasitic resistances. Moreover, it should be noted that the maximum substrate temperature is limited by the HM formation process, not the  crystallization process of the PLA in flowing water. Actually, the crystallization method could be applicable to form poly-Si on a flexible substrate of polyethylene terephthalate. 60) Therefore, we believe that these results open up a higher degree of freedom for the fabrication of thin-film TEGs, not only on a Si chip, but on flexible substrates such as glass, plastic and paper.
In conclusion, we addressed the thermoelectric properties of n-and p-type poly-Ge 0.98 Sn 0.02 layers on SiO 2 and investigated the feasibility of a poly-Ge 1−x Sn x thin-film TEG with the in-plane π-type structure integrated on a Si substrate covered with SiO 2 . The key highlight of this work also includes the sub-300°C method of the PLA in flowing water for the polycrystallization and dopant activation. A relatively high PF (maximum: 9.2 μ Wcm −1 K −2 at RT) was also achieved even for the n-type poly-Ge 0.98 Sn 0.02 layers owing to an excellent activation ratio of the Sb atoms. These results are quite informative for realizing sequential integration of poly-Ge 1−x Sn x thin-film TEGs in a 3D-IC without degradation of the underlying circuits.