Lg = 25 nm InGaAs/InAlAs high-electron mobility transistors with both fT and fmax in excess of 700 GHz

In this paper, we report an Lg = 25 nm InGaAs/InAlAs HEMT on InP substrate that delivers excellent high-frequency characteristics. The device exhibited a value of maximum transconductance (gm_max) = 2.8 mS μm−1 at VDS = 0.8 V and on-resistance (RON) = 279 Ω μm. At ID = 0.56 mA μm−1 and VDS = 0.5 V, the same device displayed an excellent combination of fT = 703 GHz and fmax = 820 GHz. To the best of the authors’ knowledge, this is the first demonstration of a transistor with both fT and fmax over 700 GHz on any material system.

T he development of terahertz (THz) microelectronics has yielded new areas of research and applications in the sub-millimeter-wave regime (sub-MMW; 300 GHz-3 THz), such as security/medical imaging systems, collision avoidance radars, next-generation transport communications, and wireless-local-area-networks. [1][2][3][4][5][6] In order to fully exploit the sub-MMW band, it is crucial to develop semiconductor transistor technologies with both current-gain cutoff frequency ( f T ) and maximum oscillation frequency ( f max ) close to 1 THz simultaneously. In this regard, both InGaAs-based high-electron mobility transistors (HEMTs) and double-heterojunction-bipolar-transistors (DHBTs) on an InP substrate are strong candidates. To date, there have been many impressive accomplishments regarding the high-frequency response of both device technologies, delivering an f T of 710 GHz in the InGaAs HEMTs 1 , an f T of 695 GHz in the DHBTs 2 , and an f max in excess of 1 THz for both. 3,4,7,8) Historically, a path to improve f T in InGaAs HEMTs was to reduce the physical gate length (L g ) down to sub-30 nm, while minimizing all of the parasitic components such as series resistance and gate-fringing capacitance. On the contrary, it was found to be essential to minimize gate resistance (R g ), gate-to-drain feedback capacitance (C gd ) and output conductance (g o ) in order to boost f max in those devices. However, this yielded significantly unbalanced highfrequency characteristics, limiting their usage. As a result, it is imperative to boost both f T and f max in a harmonious way, since this enables a wide variation of applications such as low-noise-amplifiers (LNAs) and various THz integrated circuits using a single device technology. [9][10][11][12][13][14][15][16] In our previous report, 17) we demonstrated a significant potential of using an indium-rich channel design with Hall mobility close to 13 000 cm 2 V −1 s −1 , which resulted in outstanding DC and high-frequency characteristics with L g = 87 nm InGaAs HEMTs. In this paper, we demonstrate aggressively scaled down InGaAs/InAlAs HEMTs on a 3 inch InP substrate with both f T and f max in excess of 700 GHz at the same bias condition. Key aspect was a successful reduction of L g down to 25 nm with an optimized unit process, while mitigating short-channel effects.
The epitaxial layer structure used in this work was grown on a 3 inch semi-insulating InP substrate using metal-organic chemical-vapor-deposition. From top to bottom, the epitaxial layer structure consisted of a 30 nm thick heavily-doped multilayer cap (In 0.53 Ga 0.47 As/ In 0.52 Al 0.48 As), a 3 nm thick InP etch-stopper, a 9 nm thick In 0.52 Al 0.48 As barrier/spacer with Si δ-doping, a 9 nm thick indium-rich InGaAs quantum-well channel, and a 200-nm In 0.52 Al 0.48 As buffer on the InP substrate. Details on the material growth were reported in Ref. 18. Key aspects are as follows: (i) a multi-layer cap to lower S/D ohmic contact resistance, and (ii) an In 0.53 Ga 0.47 As/In 0.8 Ga 0.2 As/In 0.53 Ga 0.47 As (1/5/3 nm) composite-channel to improve carrier transport properties. As reported previously, 18) the Hall mobility (μ n_Hall ) was measured to be 13 500 cm 2 V −1 s −1 with a two-dimensional electron gas density of approximately 3 × 10 12 cm −2 at 300 K.
The device fabrication was nearly the same as in previous report from our group. 17) This is a two-step recess process with a gate-to-channel distance, t ins , of approximately 5 nm. Source-to-drain spacing (L SD ) was scaled down to 0.8 μm, and a non-alloyed metal stack of Ti/Mo/Ti/Pt/Au (5/10/10/ 10/200 nm) was used to form S/D ohmic contact. After a gate recess process, a SiO 2 -assisted T-gate with a metal stack of Pt/Ti/Pt/Au was formed. Figure 1(a) shows a cross-sectional scanning-electron-microscope image prior to the gate metallization process. Figure 1(b) shows a cross-sectional transmission-electron-microscope (TEM) image after the gate process. The inset of Fig. 1 (b) is an enlarged TEM image of the gate foot region, indicating that the gate length (L g ) was as small as 25 nm. Figure 2(a) shows the DC output characteristics of our representative InGaAs/InAlAs HEMTs with L g = 25 nm. The devices possessed a small value of R ON = 279 Ω μm, which was due to the combination of the capping layer design and the optimized ohmic process. The contact resistance (R C ) of approximately 40 Ω μm was measured from the transmissionline-method measurement. As shown in Fig. 2(b), the same device delivered the maximum transconductance (g m_max ) of 2.8 mS μm −1 at V DS = 0.8 V. More importantly, reasonable subthreshold characteristics, such as subthreshold-swing (S) of 100 mV/decade and drain-induced-barrier-lowering (DIBL) of 120 mV V −1 , were demonstrated even in such a short-L g device. Figure 2(c) shows the measured g m of the same device as a function of drain current density (I D ) for various values of V DS . Notice that the device possessed a fairly broad range of high g m over I D , which would be highly beneficial to a diversity of applications.
The microwave characteristics of our representative InGaAs/InAlAs HEMTs were characterized from 1-50 GHz using an Agilent PNA system with off-wafer calibration. Onwafer open and short patterns were utilized to subtract padrelated capacitance and inductance components from measured scattering parameters (S-parameters). 19) Figure 3(a) plots a measured short-circuit current-gain (|h 21 | 2 ), a Mason's unilateral gain (U g ), and a maximum stable gain (MSG) after de-embedding pad-related parasitic components for the device with L g = 25 nm and W g = 2 × 20 μm at V DS = 0.5 V and V GS = 0.15 V near the peak g m bias condition. We   obtained a value of f T = 703 GHz by extrapolating the measured |h 21 | 2 with a slope of −20 dB/decade using a least-squares fit. As shown in Fig. 3(a), the measured U g did exhibit a sharp peaky behavior which was also seen in other groups' results. 3,7,8,[20][21][22] As a consequence, f max could not be directly extracted from the measured U g . Instead, we constructed a small-signal model shown in Fig. 3(b), in order to estimate f max accurately from a well-behaved U g with a single-pole system. 17,[23][24][25] It is true that there exists inconsistency between the measured and the modeled U g especially in the low-frequency regime. This is due to the fact that our small-signal model did not take the effect of impactionizations in the InGaAs QW channel into account. Nevertheless, this kind of the small-signal model has provided a reasonable estimate on f max , since the effect of the impact-ionizations diminishes as the measured frequency goes over 10 GHz. In this way, a value of f max = 820 GHz was obtained, which is identical to one from the modeled MSG/MAG. It is remarkable that the device delivered both f T and f max above 700 GHz at the same bias condition. Table I shows small-signal model parameters, together with each delay time component as defined in Ref. 24. Here, transit time (τ t ) is the carrier's transit time under the gate from the edge of the source to the edge of the drain, while extrinsic delay (τ ext ) is related to the parasitic charging delay due to extrinsic gate capacitances (C gs_ext and C gd_ext ) and parasitic delay (τ par ) to the RC time delay due to the series resistances (R S and R D ). Note that both extrinsic gate capacitances came mostly from the T-shaped gate structure. First of all, note that the excellent high-frequency response was due to a very high value of an intrinsic transconductance (g m_int ) of 4.425 mS μm −1 even in the device with L g = 25 nm, as shown in Table I. However, it should be emphasized that the portion of τ t constitutes only by 20%, indicating that a majority portion of the device's intrinsic high-frequency characteristics was contaminated with unwanted parasitic components, such as series resistances and extrinsic gate capacitances. Unless decreasing a majority portion of both τ ext and τ par , a further reduction of L g would lead to a marginal improvement in f T . Figure 4 plots the extracted f T as a function of I D for the same device with various values of V DS . Consistent with the g m against I D in Fig. 2(c), the device yielded a wide range of I D that provided f T in excess of 600 GHz. At I D of around 0.1 mA μm −1 which is a typical choice of the bias condition for most of LNA designs, our device already displays f T over 400 GHz. Finally, Table II summarizes the historical evolution of HEMT technologies, together with key results (g m , R ON , f T and f max ). Since GaAs pseudomorphic-HEMTs (PHEMTs) exhibited the first demonstration of both f T and f max over 100 GHz, 26) In x Ga 1-x As HEMTs with x > 0.53 have provided a record combination of f T and f max, 7,8,[20][21][22][26][27][28][29][30] and our results represent the first demonstration of both f T and f max over 700 GHz.
In this paper, we demonstrated an L g = 25 nm InGaAs/InAlAs HEMT with an outstanding combination of DC and highfrequency characteristics. At its heart, the indium-rich InGaAs channel was utilized with superior Hall mobility of 13 500 cm 2 V −1 s −1 at 300 K, and the gate length (L g ) was successfully scaled down to 25 nm while maintaining the electrostatic integrity of the device. In particular, the device with L g = 25 nm exhibited R ON = 279 Ω μm, g m = 2.44 ms μm −1 , f T = 703 GHz and f max = 820 GHz at V DS = 0.5 V, respectively. To the best of our knowledge, this is the first demonstration of both f T and f max in excess of 700 GHz on any transistor on any material system.  Fig. 3(a) represent a projection from the modeled |h 21 | 2 and U g with −20 dB/decade using a leastsquares fit. Table I. Small-signal model parameters of the L g = 25 nm InGaAs/InAlAs HEMT at V DS = 0.5 V and V GS = 0. 15