SOI wafer fabricated with a diamond BOX layer using surface activated bonding at room temperature

We used (100) Czochralski (CZ) 2 inch silicon wafers. The base wafer was polished to 3 mm thickness and the bonding wafer, used as a silicon layer, was polished to 500 μm thickness. When another material layer is deposited on a base wafer, the base wafer might be warped. Thus, we used base wafers that were thicker than standard wafers. These wafers were made of phosphorus-doped CZ-silicon single-crystal. Their resistivity was 5 Ω cm and their oxygen concentration was 1.2 × 10⁻¹⁸ atoms cm⁻³. As shown in Fig. 1, the base wafer was coated with nanodiamonds dissolved in water by spin-coating. The grain size of these nanodiamonds was under 10 nm, and they made up 5% of the wafer. This coated base wafer was baked at 80 °C for 3 min in air in a clean room using a hot plate. Then, a diamond layer was deposited as a BOX layer on the base wafer between 900 °C and 1200 °C using MW-CVD (Nihon Koshuha Co. Ltd, MDD-2016). Only the top surface of this diamond layer was polished by CMP. The bonding wafer was then bonded to the polished diamond layer by SAB at room temperature in ultrahigh vacuum under 1 × 10⁻⁵ Pa by connecting the dangling bonds on the surfaces of the two wafers (Mitsubishi Heavy Industries Machine Tool Co. Ltd, MWB-08-AX). These dangling bonds were formed on the top surface of the two wafers by irradiating argon ions at 1–2 keV to activate the surface of the two wafers. After bonding the two wafers, the bonded wafer was ground and polished until a silicon layer of 2 μm formed on the back side, which is opposite the wafer-bonding interface. A reference SOI wafer was fabricated using thermal oxidation and thermal bonding. A 1.5 μm BOX layer was formed on the base wafer by thermal oxidation above 900 °C. The bonding wafer was bonded to the BOX layer of the base wafer by high-temperature treatment at 800 °C for 2 h and 1150 °C for 1 h.¹⁰⁾

As shown in Fig. 1, we analyzed how binding occurred on the surface of the nanodiamond-coated base wafer after baking [step (a)]. We then observed and analyzed the diamond layer after deposition and polishing [steps (b)–(e)]. Next, we looked for voids after bonding the silicon wafer to the diamond layer [steps (f) and (g)]. Then, we evaluated the concentration of doping elements and the resistivity in the silicon layer and analyzed the diamond layer after grinding and polishing the bonding silicon wafer to the thickness of the active layer of the device [steps (h)–(j)]. After that, we evaluated the breakdown electric field of the diamond layer after fabricating actual devices in the silicon layer [steps (k) and (l)]. Finally, we evaluated the thermal conductivity of the diamond layer on the base wafer [step (m)].

2.2.1. Analysis of base wafer surface after baking nanodiamond-coated base wafer and depositing diamond layer on base wafer

2.2.2. Analysis of crystalline nature of diamond layer deposited on base wafer

2.2.3. Observation of surface and cross section of studied sample

2.2.4. Evaluation of roughness of surface of polished diamond layer of base wafer

2.2.5. Evaluation of voids after bonding silicon wafer to diamond layer of base wafer

2.2.6. Evaluation of depth profile of concentration for doping element in silicon layer after fabricating SOI wafer

2.2.7. Evaluation of depth profile of resistivity in silicon layer after fabricating SOI wafer

2.2.8. Evaluation of breakdown electric field of diamond-BOX layer

Using the device fabrication process in Fig. 2, we fabricated actual devices in the silicon layer using a test-element group (TEG). We then evaluated the breakdown voltage and electric field of the diamond layer by time-zero dielectric breakdown (TZDB) measurement²⁹⁾ while probing the TEG. We used a Keithley 237 High-Voltage Source-Measure Unit (Keithley) as the measurement system and STN-W010-D0.5-L32 probing equipment (Tiatech). The probe was made of tungsten and had a diameter of 10 μm.

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2.2.9. Evaluation of thermal conductivity of diamond-BOX layer

We analyzed the surface of the nanodiamond-coated base wafer after baking using XPS. Figure 3 shows the XPS results. Figure 3(a) shows the Si 2p spectra and Fig. 3(b) shows the C 1 s spectra. According to Fig. 3(a), Si–O bonds were detected at binding energies of 101 eV (SiO_x) and 103 eV (SiO₂).³²⁾ The Si–O bonds existed at the surface of the base substrate after baking. According to Fig. 3(b), C–O bonds were detected at a binding energy of 286.5 eV and C=O bonds were detected at a binding energy of 288 eV.^32,33) C–O and C=O bonds also existed at the surface of the base substrate. However, C–Si bonds were not detected at a binding energy of 283 eV.³²⁾ We conclude that the carbon in the nanodiamonds did not directly bond to the silicon substrate. In addition, elemental carbon was detected in 28% elemental silicon, we assumed that nanodiamond was coated at the density of 28% for the surface of base wafer.

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Figure 4 shows the OM observation results for the base wafer surface after depositing the diamond layer on the nanodiamond-coated base wafer. The thickness of the deposited diamond layer was 10 μm. Figure 4(a) shows a photograph of the 2 inch base wafer. Diamonds were deposited on the entire wafer. Figure 4(b) shows the OM observation. Diamonds were densely deposited, and the diamond grain size was under 10 μm. These grains were smaller than those of the diamond layer deposited by scratching using diamond powder.³⁴⁾

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Figure 5 shows the results of XRD analysis for the deposited diamond layer. (111), (220), and (311) diffraction peaks were detected.³⁵⁾ The deposited diamond layer mainly consisted of (111) and (220) single crystals. We assume that polycrystalline diamond was deposited on the base wafer. In addition, Fig. 6 shows C1s photoemission spectra for the surface of the diamond layer deposited on the base wafer obtained by XPS analysis. The sp³ peak at 285.4 eV was mainly detected.³⁶⁾ Because native oxide was formed on the diamond layer, C–O bonding was also detected. Therefore, we concluded that the polycrystalline diamond layer was deposited on the base wafer using our proposed flow (Fig. 1).

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After the diamond layer was polished by CMP until its thickness was reduced from 10 to 8 μm, we evaluated the flatness of the polished surface using the AFM method. The average roughness (Ra) was 2–3 nm over 400 μm². This value is sufficiently low to enable the bonding of another wafer and layer by SAB at room temperature in vacuum.³⁷⁾

Figure 7 shows an IR transmission image of the above-mentioned sample after bonding a silicon wafer to the polished diamond layer by SAB at room temperature under a pressure of 1 × 10⁻⁵ Pa. There were no voids with gaps of over 200 nm in the wafer; this observation method can only detect gaps of over 200 nm. The silicon wafer was thus successfully bonded to the diamond layer by SAB.

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We also observed the bonded interface through cross-sectional OM and TEM micrographs of the chips obtained after dicing the bonded wafer at its center. Figures 8(a) and 8(b) show cross-sectional images obtained by OM observation and TEM observation, respectively. There were no voids with gaps of over 1 μm over a wide area, as shown in Fig. 8(a), and there were no voids with gaps of over 1 nm in the bonding region, as shown in Fig. 8(b). Therefore, we found that a silicon wafer can be bonded on a diamond layer of a base wafer without voids with gaps of over 200 nm.

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Because the devices were fabricated in a silicon layer on a BOX layer, it is important that the doping element concentration has a constant depth profile in the silicon layer. Thus, the depth profile of the concentration of phosphorus, an n-type conductor, was analyzed from the surface of the silicon layer to the bonding interface (the surface of the BOX layer) in the studied sample and reference sample (SOI wafer) by SIMS analysis.

Figure 9 shows the results of the SIMS analysis. The horizontal axis is the distance from the bonding interface and the vertical axis is the phosphorus concentration obtained from the SIMS analysis. For the studied sample [Fig. 9(a)], the concentration of phosphorus was constant from the top surface of the silicon layer to the bonding interface. However, for the reference sample [Fig. 9(b)], the concentration of phosphorus decreased from a depth of 0.2 μm to the bonding interface. We assume that phosphorus outdiffused from the silicon layer to the BOX layer in the reference sample during the bonding of the silicon wafer to the BOX layer at high temperatures of over 800 °C.

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Because the devices were fabricated in a silicon layer on a BOX layer, it is also important that the resistivity has a constant depth profile in the silicon layer. The resistivity profiles of the studied sample and reference sample (SOI wafer) were investigated from the surface of the silicon layer to the bonding interface (the surface of the BOX layer) by SR measurement.

Figure 10 shows the results of the SR measurement. The horizontal axis is the distance from the bonding interface and the vertical axis is the resistivity obtained by SR measurement. For the studied sample [Fig. 10(a)], the resistivity was constant from the top surface of the silicon layer to the bonding interface.

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However, for the reference sample (SOI wafer) [Fig. 10(b)], the resistivity increased from a depth of 0.8 μm to the bonding interface between the silicon layer and the BOX layer. At the interface, the resistivity was about 1 × 10⁴ times that in the region of constant resistivity between depths of 0.8 and 2.0 μm. This might have been due to the outdiffusion of the doping element (phosphorus) from the silicon layer to the BOX layer during thermal bonding at high temperatures of over 800 °C. According to Fig. 9(b), the concentration of phosphorus decreased by a factor of 10 from a depth of 0.2 μm to the bonding interface, thus increasing the resistivity by a factor of 10. Therefore, this increase in resistivity cannot be explained by the decreasing concentration of phosphorus. We consider that this increase in resistivity was caused by the formation of positive fixed charges³⁸⁾ in the BOX layer.

Figure 11 shows a photograph of the studied sample after devices were fabricated on it. Although the maximum temperature was 1000 °C, the silicon layer was not removed from the diamond layer during the fabrication of the devices. Figure 12 shows a cross-sectional TEM image of the studied sample after devices were fabricated on it. No gaps were generated at the bonding interface, and amorphous layers near the bonding interface were recrystallized after fabricating the devices. We found that the bonding strength obtained with the SAB technique was sufficient to fabricate the devices.

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We measured the breakdown electric field of the BOX layer of the studied sample and the reference SOI sample using TZDB, which is a voltage-step-stress method. As a silicon substrate is supplied 0 V, the metal connected to the silicon layer has an additional input voltage of 0.1 V. Figure 13 shows the equivalent circuit schematic for the SOI wafer, where R_Si is the resistance of the silicon layer, R_BOX is that of the BOX layer, R_Sub is that of the base wafer, and R_all is the resistance from the top surface to the back side of the base wafer. Because R_Si, R_BOX, and R_Sub are connected serially,

$$\begin{eqnarray}&&{{R}}_{{\rm{all}}}={{R}}_{{\rm{Si}}}+{{R}}_{{\rm{BOX}}}+{{R}}_{{\rm{Sub}}}.\end{eqnarray} \tag{ 1 }$$

As V_BOX is the voltage applied to the BOX layer and V_in is the voltage input to the silicon layer, V_BOX can be calculated using Ohm's law,³⁹⁾

$$\begin{eqnarray}&&{{V}}_{{\rm{BOX}}}={{V}}_{{\rm{in}}}\,* \,{{R}}_{{\rm{BOX}}}/({{R}}_{{\rm{Si}}}+{{R}}_{{\rm{BOX}}}+{{R}}_{{\rm{Sub}}}).\end{eqnarray} \tag{ 2 }$$

We can calculate R_Si and R_Sub by multiplying the resistivity and thickness. It is necessary for calculating R_BOX to measuring the resistivity of diamond layer. However, the contact resistivity between the probe of the measuring equipment and the diamond layer increased, using the four-terminal method and SR method. Thus, it is difficult to measure the resistivity of the diamond layer.

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From Eq. (1),

$$\begin{eqnarray}&&{{R}}_{{\rm{BOX}}}={{R}}_{{\rm{all}}}-({{R}}_{{\rm{Si}}}+{{R}}_{{\rm{Sub}}}).\end{eqnarray} \tag{ 3 }$$

Figure 14 shows the breakdown voltage and electric field for the studied sample and reference sample obtained by TZDB measurement. The measured area of the silicon layer was 1 mm² as shown in Fig. 2(b). We calculated R_all from the I–V curve in Fig. 14(a). When the current density exceeds 2 × 10⁻¹⁰ A cm⁻², we define R_all by the following equation in terms of the input voltage V_t and current I_t

$$\begin{eqnarray}&&{{R}}_{{\rm{all}}}={{V}}_{{\rm{t}}}/{{I}}_{{\rm{t}}}.\end{eqnarray} \tag{ 4 }$$

Consequently, R_all is 4.6 × 10¹¹ Ω, R_Si is 1.0 × 10⁻³ Ω, and R_Sub is 1.5 Ω.

When R_BOX is much larger than R_Si and R_Sub, R_BOX satisfies

$$\begin{eqnarray}&&{{R}}_{{\rm{BOX}}}\fallingdotseq {{R}}_{{\rm{all}}}\end{eqnarray} \tag{ 5 }$$

from Eq. (1). V_BOX can be calculated from Eqs. (1), (2), and (5) as

$$\begin{eqnarray}&&{{V}}_{{\rm{BOX}}}\fallingdotseq {{V}}_{{\rm{in}}}.\end{eqnarray} \tag{ 6 }$$

In addition, we calculated the electric field by dividing V_BOX by the thickness of the BOX layer, the results of which are shown in Fig. 14(b). The breakdown electric field was defined as the input voltage at which the leakage current reached 1 × 10⁻⁴ A cm⁻². The breakdown electric field of the studied sample was 1 MV cm⁻¹. Because the breakdown electric field of a polycrystalline diamond is about 1 MV cm⁻¹,^40,41) we consider that this result is reasonable. The breakdown electric field of the reference sample was 8.0 MV cm⁻¹. Because the breakdown electric field of a thermal oxide is generally 8–15 MV cm⁻¹,²⁹⁾ this result is also reasonable. We consider that the lower breakdown electric field of the studied sample than that of the reference sample was due to the grain boundaries in the polycrystalline diamond layer.⁴²⁾ We will attempt to study this issue in the future.

We evaluated the thermal conductivity of a base wafer with a diamond-BOX layer using a TCi thermal conductivity analyzer to transiently measure the resistivity at the surface of a sample after it was heated. We evaluated three samples: a silicon substrate as a reference sample, a SiO₂ layer on a silicon substrate as another reference sample, and a diamond layer on a silicon substrate as the studied sample. The thickness of the base wafers and the silicon substrate was 500 μm and the thickness of the BOX layer was 4 μm.

Figure 15 shows the thermal conductivity of the three samples, which were 120 W mK⁻¹ for the reference sample with the SiO₂ layer, 348 W mK⁻¹ for the studied sample with the diamond layer, and 291 W mK⁻¹ for the silicon substrate without the BOX layer. The thermal conductivity of the studied sample was almost three times higher than that of the reference sample with the SiO₂ layer and higher than that of the silicon substrate without a BOX layer.

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According to the XPS analysis (Fig. 6), the studied polycrystalline diamond layer mainly has an sp³ structure and does not have an sp² structure. Thus, the studied polycrystalline diamond layer has a similar thermal conductivity to the single-crystal diamond.

Because SiO₂ has much lower thermal conductivity than silicon,⁴³⁾ and diamond has much larger thermal conductivity than silicon,⁴⁴⁾ we conclude that the results in Fig. 15 are reasonable. Therefore, the studied sample has high thermal conductivity and the diamond-BOX-SOI wafer will have similar thermal conductivity to a silicon substrate without a BOX layer.

Diamond cannot be grown on a substrate of a different material without seeding elemental carbon. The seeding techniques are generally involve scratching the substrate using diamond powder^13,15,16) and implanting carbon ions into the substrate by BEN.¹⁴⁾ In this work, we did not use these seeding techniques to avoid damaging the surface of the base wafer. As an alternative, we spin-coated²⁴⁾ nanodiamond on the base wafer and baked the spin-coated base wafer.

According to the XPS results for the base wafer surface after baking the spin-coated base wafer shown in Fig. 3, we found that C–Si bonds do not exist on the base wafer, and the elemental carbon in nanodiamond does not connect directly to the elemental silicon in the base wafer. Then, we found that C–O and Si–O bonds existed on the surface of the base wafer after baking the spin-coated base wafer. Thus, we assumed that the elemental carbon on the surface of the base wafer bonded with the elemental silicon on the surface of the base wafer through the elemental oxygen, and we propose this seeding mechanism, that is thermal-treatment-wafer-bonding^45–49) through the elemental oxygen after vaporizing H₂O.

Figure 16 shows the mechanism of diamond seeding. In step (a), the nanodiamonds contained in water are spin-coated on a base wafer. Because water exists around each nanodiamond, the nanodiamond does not come in direct contact with the base wafer in this process. In step (b), the base wafer is baked at 80 °C. Only the wafer (H₂O) coating the nanodiamonds is vaporized, and the carbon in the nanodiamonds is weakly bonded to the oxygen in the native oxide layer. In step (c), diamonds are deposited on the base wafer between 1000 °C and 1200 °C. In this process, the carbon is strongly bonded to the oxygen in the native oxide layer on the base wafer.

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As shown in Fig. 8(b), according to the results of cross-sectional HR-TEM observation of the interface bonded by SAB, amorphous layers existed above and below the bonding interface. The thickness of these layers was about 5 nm. We found that these amorphous layers were formed by argon ion irradiation performed to induce SAB.^50–53) This argon ion irradiation generated dangling bonds on the surface of the polycrystalline diamond layer and the bonding wafer at the same time. Figure 17 shows the mechanism of bonding between the polycrystalline diamond layer and bonding wafer for the studied sample (diamond-BOX-SOI wafer). In step (a), the surfaces of the bonding wafer and polycrystalline diamond layer are sputtered by argon ion irradiation in ultrahigh vacuum, and the dangling bonds are generated at these surfaces. Because these dangling bonds are stable in ultrahigh vacuum, the surfaces of the bonding wafer and polycrystalline diamond layer have dangling bonds, which can connect with other elements in ultrahigh vacuum. Thus, in step (b), when these bonds come close to each other, the dangling bonds at the elemental silicon in the bonding wafer become connected to the elemental carbon in the polycrystalline diamond layer.

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Liang and co-workers reported the bonding of a single-crystal silicon substrate to a single-crystal diamond substrate by SAB.⁵³⁾ They showed that the argon ion-irradiated region of the single-crystal diamond substrate had σ-connect-ions and π-connect-ions by electron energy loss spectroscopy (EELS), and that it had sp³ and sp² bonds and no C–O bonds by XPS analysis. The σ-connect-ions and sp³ bonds showed that the single-crystal diamond was a cubic crystal system, and the π-connect-ions and sp² bonds showed that the graphite had dangling bonds. The failure to detect C–O bonds indicated the removal of the native oxide layer on the diamond layer. Thus, the argon ion-irradiating could remove native oxide layer on diamond layer, maintained single-crystal diamond and could form dangling bonds on diamond layer. We clarified that the dangling bonds of the irradiated diamond substrate connected to those of the irradiated silicon substrate.

We also evaluated the crystal condition and bonding states in the bonding region of the polycrystalline diamond layer using EELS and XPS. Figure 18 shows the results of EELS analysis of the polycrystalline diamond layer and its bonding interface. Figure 18(a) shows the analyzed points. As shown in Fig. 18(b-1), a σ* peak was detected at 292 eV for the polycrystalline diamond layer, whereas a σ* peak was detected at 292 eV and a π* peak was detected at 286 eV near the bonding interface of the polycrystalline diamond layer, as shown in Fig. 18(b-2).

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To evaluate how the silicon layer bonded to the polycrystalline diamond layer, only the silicon layer on the diamond layer of the studied sample was removed by CMP and etching. Then, we analyzed the top surface of the diamond layer after the SAB process by XPS. Figure 19 shows the results of the XPS analysis. According to the spectra in Fig. 19(a), sp³ bonds were mainly detected, although sp² and C–Si bonds were also detected.^32,36) Figure 19(b) shows additional spectra obtained after depositing a diamond layer on the base wafer (before the SAB process, Fig. 6). The surface of the diamond layer does not have sp² or C–Si bonds after depositing the diamond layer but has sp³ and C–O bonds.

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These results are the same as those reported by Liang and co-workers.⁵³⁾ We clarified that the native oxide layer on the diamond layer was removed and that the sp² structure was generated on the surface of the diamond layer by irradiating argon ions to the surface of the diamond layer. Moreover, C–Si bonds were generated by connecting the activated elemental silicon in the silicon wafer to the activated elemental carbon in the diamond layer. Therefore, we assume that our mechanism shown in Fig. 17 is reasonable.