Abstract: The heavy ion experiment was carried out for the static random array memory (SRAM) fabricated with the 22 nm fully depleted silicon on insulator (FDSOI) technology. The single event upset (SEU) and multiple cell upset (MCU) sensitivities of FDSOI SRAM with different radiationhardened designs were compared. The characterization and mechanism of MCU induced by readwrite errors were analyzed. The influence of the substrate bias voltage on FDSOI SRAM SEU sensitivity was revealed. The results show that for five investigated FDSOI SRAMs, the antiSEU capability is from weak to strong in order of 8T SRAM2, redundancydesigned SRAM1, dual interlocked cell (DICE) SRAM3 or SRAM4, and dualDICE SRAM5. The memory arrays of the three DICEtype FDSOI SRAMs have better antiMCU performance than those of the other two SRAMs. Although the memory arrays of DICEtype FDSOI SRAMs had strong antiMCU capability, the influence of readwrite errors inducing MCU on DICEtype FDSOI SRAMs could not be ignored, and the influence is found to be more serious with the increase of SRAM operation frequency. The substrate bias voltage affects the FDSOI SRAMs upset sensitivity by controlling the parasitic bipolar amplification effect.