This thesis presents a non-interleaved, high speed, 6-bit data converter pair design. Two test chips have been realized in TSMC 130nm CMOS Mixed-Mode RF and UMC 90nm CMOS Mixed-Mode technology, respectively. Simulation results show the 130nm one can achieve a 5GS/s sampling rate and the 90nm one can achieve a 10GS/s sampling rate. The proposed Analog-to-Digital converter (ADC) is a flash type ADC. The wide bandwidth and low power comparators were realized by active feedback pre-amplifiers (PreAmps). Furthermore, we added the differential negative capacitors to reduce the total delay of the cascade PreAmps. Averaging and interpolating skills were applied to the outputs of the PreAmps so as to reduce the offsets and the number of the amplifiers. The Digital-to-Analog converter (DAC) is a current-steering one. The digital circuits of the data converter pair are implemented with the current mode logic (CML) gates which alleviate the issue of severe power-ground bouncing compared with conventional CMOS logic implementation. In addition, the CML gates not only have less gate delays, but also are suitable for low voltage operation. To address the difficulty of conducting at-speed tests, we added the design-for-testability (DfT) circuitry. The measurement results of the 130nm test chip show that in the at-speed test mode, the data converter pair achieves an SNR of 46.1 dB and an SNDR of 36.4 dB with the 0.5GHz sinusoidal inputs at 3GS/s. It corresponds to an ENOB of 5.7 bits. The 130nm test chip including the DfT circuitry totally consumes 790 mW from a 1.2V supply. Besides, the measurement results of the 90nm test chip show that the data converter pair achieves an SNR of 29.0 dB and an SNDR of 24.2 dB with the 1.1GHz sinusoidal inputs at 10GS/s. It corresponds to an ENOB of 3.7 bits. The 90nm test chip totally consumes 448 mW from a 1.0V supply.