Along with the increment of the wafer size and the numbers of the metal layers, plus the transistors and the metal lines constantly diminished. The technology of semi-conductor VLSI manufacturing process, which does away with the rough and uneven body, presents its necessity. The CMP is a technique of the global planarization, and each factory of semi-conductor has depended on. It’s making use of the slurry for oxidizing the outstanding part of the dipping layer of the wafer surface first and then polishing the gate oxide by the carrier, thus it can provide a flat surface for the next layer. The CMP also needs a nice bit of factors to match mutually. Thus the factors of how to increase the flatness have become the top lesson to the global planarization. Further it has something to do with the raise of good rate, the increment of productivity and the cost down of production. The results will decide the quality of the follow-up process and the reliability of products since the STI‘s main purpose is to isolate from the cells. The objective of this thesis emphasizes at promoting and improving the global planarization of shallow trench isolation (STI) process and putting forward two methods takes into study: 1. Addition extreme edge HDP etch process to promote the global planarization. 2. Change the STI-CMP carrier speed without extreme edge HDP etch process and discuss the effects of the global planarization. Finally we compare the relation of these two methods with the produce and good rate of the factory of semi-conductor.