Si MOSFET has been scaled down to nanometer to achieve high speed operation and high device density. However, the short-channel effects are important issues that can be released by tri-gate FinFET. Moreover, the quantum confinement effect can reduce the phonon scattering and hence enhance the carrier mobility. With high dielectric constant gate oxides, the gate control capability can be further improved. In order to develop even higher speed devices, III-V compound MOSFET has attracted much attention from higher electron mobility compared with that of Si. In this study, using the nanoimprint lithography to fabricated III-V compound nanowire has been well investigated. Moreover the surface passivation of III-V with (NH4)2S treatment could prevent it from oxidizing after cleaning for improve the interface properties and Fermi level pinning. We made of improvement quality for existing titanium oxides, using double stack of titanium oxide (TiO2) and aluminum oxide (Al2O3) by ALD. ALD has self-cleaning property which could improve interface quality between oxide and substrate, the leakage current densities are 7.31X10-7, 3.11X 10-6 and 7.40X10-7 A/cm2 at ±2.0MV/cm, respectively.