With the advances in integrated circuit(IC) process, IC design issues that need to be handled will be more difficult. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce the cost of IC design and manufacturing, structured ASIC emerges as a new design alternative. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Memory IP is an important component for structured ASIC. One of the most widely used is the static random access memory (SRAM). In this thesis, we propose a via-configurable logic block (VCLB) which can be use to implemented all the elements of memory IP. We also develop a SRAM compiler to automatically generate SRAM with our VCLB and routing fabric.