This work proposed a domain specific toolchain for pre-processing and assume that the application is the multivariate quadratic equations set implementation on FPGA. The purpose is to exhaustively apply the domain knowledge of multivariate quadratic equations to help the generic tools to perform well, benefitting breadth from generic tool and depth from domain knowledge. Two heuristics are integrated in the toolchain: greedy heuristic to construct a few k-feasible fanout free cones (FFCs) close to fanin for a equations to reduce structural-bias, and common subexpression extraction to extract the sharing expression among equations for area reuse. The goal of the heuristics is to generate a well-formed circuit in BLIF format, and the file will be further processed by the state-of-the-art academic software synthesis system ABC to perform structural LUT mapping. After mapping, the output from ABC is also a BLIF format file where each sub-circuit block represents a LUT, and the final translation to verilog module is only naive one-to-one. The experimental result shows that for area-oriented mapping, our toolchain can reduce the area up to 11.2% comparing to previous work.