87.-Design-and-performance-measurements-of-a-parallel-machine.pdf (824.29 kB)
DESIGN AND PERFORMANCE MEASUREMENTS OF A PARALLEL MACHINE FOR THE UNIFICATION ALGORITHM
Unification is known to be the most repeated operation in logic programming and PROLOG interpreters. To
speed up the execution of logic programs, the performance
of unification must be improved. We propose a parallel unification machine for speeding up the unification algorithm.
The machine is simulated at the register transfer level and
the simulation results as well as performance comparison
with a serial unification coprocessor are presented.