Mechanical Characterization of Black Diamond (Low-k) Structures for 3D Integrated Circuit and Packaging Applications

© 2012 Nagendra Sekhar, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Mechanical Characterization of Black Diamond (Low-k) Structures for 3D Integrated Circuit and Packaging Applications


Introduction
As Integrated Circuit (IC) technology scales down into the nanotechnology regime, it allows millions of active components to be fabricated on a single chip in accordance with the historical trend of Moore's law. Integration of all these active elements on a single IC, multilevel on-chip interconnect system must be developed in BEOL (Back End of the Line) technology [1]. Accordingly, to meet the industry requirements of scaling for improved performance, semiconductor technologies are forced to move from well-established Al/SiO2 interconnect technology to Cu/low-k (Copper/low dielectric constant) technology [2][3]. The main objective of this transition is to reduce cross talk noise between metal lines, propagation delays and power dissipation from RC delay. Copper and low-k inter metal dielectric layers are used as multilevel interconnects to enhance the speed of logic devices. Amongst the available low-k materials, Black diamond TM (BD, low-k, SiOC:H) has been considered as potential inter metal dielectric material for integration in ULSI (Ultra Large Scale Integration) due to its better electrical and dielectric properties. But in dielectric material processing the key issue is the trade-off between dielectric property and mechanical strength. Hence it is very important to study the mechanical properties of BD films and Cu/BD stacks.
There are four interdependent properties which are responsible for the mechanical reliability of thin film structures and they are elastic modulus, hardness, fracture toughness and interfacial adhesion [4]. Both theoretical and experimental studies recommend that hardness and elastic modulus are the two key material characteristics affecting the CMP process [5]. Generally, mechanical properties of thin films differ from those of the bulk materials. This is mainly attributed to their microstructure, interfacial mismatch stresses and molecular restructuring of the films. Parameters used to characterize the mechanical strength of BEOL interconnect materials include hardness, elastic modulus and adhesion/cohesion strength. Interfacial adhesion is the most important property to ensure the thermo-mechanical integrity of Cu/low-k stacks. Interfacial adhesive failure may occur during fabrication processes such as CMP and high temperature curing steps. In addition, delamination or cracking can also be observed during electronic packaging processes like reflow process, flip-chip bonding and back grinding due to thermo-mechanical stresses. This chapter further discusses on mechanical behavior of BD thin films of different thicknesses, single and dual dielectric stacks with Ta & TaN barriers. Nanoindentation experiments with continuous stiffness measurement (CSM) attachment have been performed on different BD film stacks to assess the multi-layer effect on the mechanical behavior of BD films. Effect of wafer backgrinding on the active side of the low-k structures have been studied using the Nanoindentation method as wafer backgrinding is one of the key technologies paving way to high performance three-dimensional (3D) microelectronic packages.

Low-K dielectric materials for BEOL (Back End of the Line) multilevel interconnect and 3D Integration applications
The contribution of the R-C delay by conventional multilevel interconnects scheme increases as the IC fabrication technology moving into further miniaturization. The introduction of Cu/low-k interconnect technology into BEOL, has progressively enhanced this condition when compared to the conventional Al/SiO2 technology by reducing R-C delay in between interconnect lines. [6][7]. In addition to migrating to Cu/low-k multilevel interconnects at chip level, microelectronic industry is more focused on 3D IC integration and 3D packaging of chips at system level. In recent times, three-dimensional (3D) IC integration and packaging is gaining more attention because of its innovativeness, high performance, high functionality, and ability to reduce size of the final product. The major applications of the 3-D packaging include digital and mixed-signal electronics, wireless, electro-optical, MEMS and other integration technologies. At this juncture, the key technologies supporting the 3-D packaging, are as: through silicon vias (TSVs), wafer thinning or back grinding, precision alignment of wafer to wafer or chip to wafer, and wafer to wafer or chip to wafer bonding [8]. Among these key technologies, wafer thinning plays a vital role in the 3D packaging integration, as it allows to accommodate or stack more dies in one package and ultimately results in the reduction of package size. Besides the reduction of package size, the stacking of thin chips provides many other advantages, such as, more functionality per package and improved heat dissipation. Electronic packaging industry has to put a lot of R&D efforts and spend millions of dollars on the wafer thinning technologies as there is no manufacturing technology available for directly producing the ultra-thin wafers [9]. That is why in the past years, many wafer thinning methods, such as mechanical grinding, chemical mechanical polishing (CMP), wet etching and atmospheric downstream plasma (ADP), dry chemical etching (DCE) have been evolved. So far many researchers have extensively studied wafer thinning/back grinding processes in terms of die strength by assessing the quality of the grinded surface [10].
In the recent years, many researchers have extensively assessed the quality of back grinding process with the help of die strength evaluation. Die strength of the thinned wafer can be evaluated by using the different mechanical testing techniques such as three point bend test, four point bend test, ball on ring test, ball breaker tests and ring-on-ring tests. The mechanical tests are greatly influenced by several processes and material parameters such as surface roughness or finish, degree of thinning, stress relief process, quality of the dicing edge [11][12][13][14][15]. However the literature available related to the effect of grinding processes on the active side of the die/chip is limited, and this necessitates a focused study on the effect of wafer back grinding on the active side of chip. For the first time we have studied the effect of back grinding processes on the active side of low-k stack by using Nanoindentation method. Usually active side of the chip is a few microns in thickness, and it cannot be studied using those methods which are being used for conventional die strength evaluation. Therefore, we have chosen sophisticated method like nanoindentation technique for mechanical characterization of low-k films.

Different types of low-k materials
In the recent past, many low-k materials have been developed, and they can be broadly classified into Si-based and non-Si based. Si-based materials can be further classified into Sibased and silsesquioxane (SSQ) based, which include hydrogen-SSQ (HSSQ) and methyl-SSQ (MSSQ). Non-Si based low-k materials can be further divided into two groups, polymer based and amorphous carbon. Several types of low-k materials with varied low-k values and different deposition methods are being used in the IC fabrication technology. Table 1 lists the contemporary deposition techniques together with the k value of various silicon based, non-silicon based and polymer dielectric material candidates for the 0.13μm and 0.1μm technology nodes.
In silica based dielectric materials, usually tetrahedral silica is the elementary unit. Each silicon atom is at the center of the tetrahedron of oxygen atoms as shown in Fig. 1 (a). Typically Si based dielectric materials are dense structures with higher chemical and thermal stability. In silica based materials, dielectric constant (k) value can be lowered by replacing the Si-O bonds with Si-F bond, producing fluorinated silica glasses (FSG) or doping with C by introducing CH3 groups [7].
Black diamond (BD) is one of the popular low-k materials and it is a trade mark of CVD processed dielectric material, introduced by Applied Materials Inc. [17]. It is silica based dielectric material, obtained by doping of silica with -CH3 groups as shown in figure Fig. 1 (b) and it has chemical formula SiOC:H. It is also called hybrid dielectric material as it contains both organic (-CH3) and inorganic (Si-O) constituents. The dielectric constant (k) value of silica based dielectrics ranges from 2.6 to 3. Typically BD thin films are fabricated by using the Chemical Vapor Deposition (CVD) method near room temperature using organosilane precursor in the presence of oxygen as oxidant. The lower density of the BD films is achieved by introducing network terminating species (-CH3) into the Si-O matrix [19]. The density and dielectric value of the BD films can be altered by the selection of terminating groups in silica network. Empirically, a larger terminating group gives lower density, because it acts as a network terminating group only and it is not part of the Si-O network. Therefore BD films retain many of the useful thermo-mechanical properties of silicon oxide. The summary of properties of BD films is given in Table 2. BD films can achieve bulk dielectric constant of around 2.5 to 2.7, and integrated ILD stack dielectric constant of <3 [20]. The glass transition temperature of the BD is well above 450°C. The dielectric constant of the BD films can be lowered mainly by introducing constitutive porosity into the microstructure [21]. By proper selection of the compatible barriers layers, thermal and mechanical properties of BD films provide evolutionary pathway to Cu/low-k interconnect technology.

Required properties of low-k materials for integration
For successful integration of low-k materials into the BEOL interconnects, besides having low dielectric constant it should be chemically, mechanically and thermally stable in the system. Every IC fabrication node technology demands low-k materials with lower dielectric values and with optimum physical properties as summarized in Table 3. Choosing a new low-k material with optimal electrical, thermal and mechanical properties for current interconnects and IC fabrication technology is very crucial. As mentioned earlier, lower dielectric constants are obtained by modifying of the molecular structure of the materials, which ultimately affects the mechanical and thermal properties of the low-k materials. Good thermal stability and low coefficient of thermal expansion is needed to prevent both, damage to the film and, property changes during subsequent thermal processing. The bulk dielectric constant of the ILD stack, when low-k film is stacked with barrier layers and liners (SiC and SiN) should be less than 3.0.

Electrical isotropic k < 3 @ 1MHz
Chemical No material change when exposed to acids, bases and strippers

Barriers and adhesion promoters for Cu/low-k structures
BEOL multilevel interconnect structures comprise varieties of materials, such as Cu, low-k materials, oxides and nitrides. Copper interconnects in BEOL technology have some challenges such as, poor adhesion to dielectric materials and diffusion of copper into silicon substrates. Copper easily reacts with silicon and forms copper silicide at low temperatures [22][23]. Traces of copper in silicon substrate will cause adverse effect on device operation. Most of the Interconnect metals (e.g. Cu, Ag, Au and W) except Al; do not bond well to underlying substrate and ILD. Therefore, the use of diffusion barrier layers and adhesion promoters between copper and underlying silicon substrate in ICs is mandatory. An ideal diffusion barrier material should also act as good diffusion barrier and adhesion promoters.
Diffusion barriers under consideration are metal nitrides, carbides and borides, and metals such as Ti, Ta, and W. Diffusion barrier should be immiscible and non-reactive with copper.
As stated by the studies, sputtered Ta and TaN films act as excellent diffusion barrier layers in Cu/low-k multilevel interconnects [24][25]. In the present investigation Ta, TaN, SiC and SiN are studied as barrier layers/cap layers in Cu/low-k stacks. SiC and SiN diffusion cap layers also acts as etch stops during the BEOL processes. Silicon nitride is widely used as cap layer; first, because it acts as an excellent barrier to copper and second, because of its etch selectivity to oxides.

Mechanical characterization of low-k structures by using nanoindentation
Currently most of IC fabrication technology has been migrated to Cu/low-k interconnect technology, as there is an increase of RC delay associated with the conventional Al/SiO2 interconnects used in the miniaturization of IC technology. This technology transition brings several integration challenges for the Cu/low-k interconnects because of poor thermal and/or mechanical properties of low-k thin films and Cu/low-k stacks [1]. Hence, it is very important to study the mechanical properties of different Cu/low-k structures to evaluate the device reliability. In the present investigation, mechanical properties of various Cu/lowk structures are studied by using nanoindentation technique.
The desired 'k' value of the low-k films can be attained by modifying the molecular structure of the low-k film or by introduction of organic or inorganic groups into the base structure [7]. Mechanical reliability and dielectric constant of the low-k materials are mutually dependent and have inverse relation. In case of SiO2 based low-k materials, dielectric constant strongly depends on the density of the material, which in turn also depends upon the amount of porosity introduced, as shown in Fig 2 [27]. In chemical vapor deposition (CVD) based low-k materials, dielectric constant is decreased by the introduction of terminal methyl (-CH3) groups, that will break the Si-O network and create nanopores. As the concentration of Si-O bonds decreases, percentage of pores and density non-uniformity increases, ultimately increasing the probability of mechanical failure of low-k films.
In IC fabrication technology, low-k material selection and its integration into BEOL is very crucial and it should withstand chemical mechanical polishing (CMP) without any failures. In microelectronic industry many researchers have been actively working toward finding threshold values of hardness and elastic modulus that can provide Cu/low-k system the ability to withstand CMP and wire bonding processes [28][29][30]. Researchers at Motorola [43] have concluded that passing the CMP process of low-k material is not a simple factor of modulus, hardness, adhesion or toughness, but a combination of all of these properties. As   stated before, the mechanical properties of low-k films depends on chemical structure, amount of porosity and composition, Elastic modulus and hardness values of the different dielectric thin films varies from 2 to 14 GPa and 0.5 to 7 GPa respectively [41][42][43][44][45]. Volinsky et al [1] have found a linear relationship between hardness and elastic modulus for silicate low-k dielectric films in nanoindentation testing with continuous stiffness measurement (CSM) attachment. In nanoindentation testing, mechanical response of low-k films is different from the metallic films and usually exhibits little or no plasticity [27]. Hardness and elastic modulus values of various low-k films and Cu/low-k stacks were tested with nanoindentation technique by many researchers and some of those results have been summarized in table 4. Based on the extensive literature survey and the present work, it is observed that the mechanical properties of various films and Cu/low-k stacks depend on many factors, more importantly the amount of porosity (Constitutive and Subtractive), composition, molecular structure, thickness, type of stack and diffusion barrier.

Sample preparation
Materials used in the present work include BD thin films, oxide, nitride and barrier layers. Black diamond, oxide, SiC and SiN films were prepared by using PECVD technique. Sputtering technique was employed to deposit the copper seed (150 nm), Ta and TaN layers. Copper film of 1μm thickness was deposited by electroplating process. Different stacks of these layers were deposited by different experimental techniques. All thin film samples were prepared on 8" Si (100) wafer in semiconductor fabrication plant of class 1000 clean room environment. A thin oxide layer of thickness about 5 nm is deposited on the surface of silicon substrates to improve the adhesion between the substrate and the low-k thin films.

Continuous Stiffness Measurements (CSM)
This technique was introduced in the year 1989 by Oliver and Pethica [36][37]. The CSM technique developed over the last decade by researchers offers numerous advantages. It has the unique advantage of providing mechanical properties as a function of penetration depth. Calibration and testing procedure take very less time as there is no need for multiple loading and unloading. At high frequencies it allows to avoid obscure effects of the samples like creep, viscoelasticity and thermal drift, which cause much problem in the conventional calibration method. It allows us to measure the effect of contact stiffness changes and damping changes at the point of initial contact [38]. In CSM nanoindentation technique the contact stiffness is measured during loading of the indentation test and there is no need for separate unloading cycles. This is an ideal method to determine contact stiffness and it can measure at very small penetration depths. Hence this method is unique to measure mechanical properties of thin films of few tens of nanometers. It has an additional advantage that if the specimen shows viscoelastic behavior, the phase difference between the force and displacement signals gives idea about the storage and loss modulus of the specimen [26].
In nanoindentation experiment, the CSM technique is carried out by applying a harmonic force at relatively high frequency (69.3 Hz), which is added to increasing load, P, on the loading coil of the indenter as shown in Fig. 3. The applied current that determines the nominal load of the indenter is very small, which results oscillations to the indenter with a frequency related contact area and stiffness of the sample [39].
This technique accurately measures displacements as small as 0.001 nm using frequency specific amplification. To determine the contact stiffness of the sample, the dynamic response of the nanoindenter has to be determined. A dynamic model which is used in CSM system is shown in Fig. 4. Major components of the dynamic model are the mass of the indenter, the spring constant of the leaf springs that support the indenter, the stiffness of the indenter frame and the damping constant due to the air in the gaps of the capacitor displacement sensing system.
And the phase angle, φ between the driving force and the displacement response is

Mechanical characterization of BD thin films with varying thickness
Thickness of the thin film structures used in the BEOL interconnects continue to decrease as the chip size decreases. Usually, thickness of the dielectric film has small effect on electrical properties [40], but it has significant influence on the mechanical properties of the film. Hence, it is very important to study the mechanical properties of these films of minute thicknesses. For this study, BD thin films of six different thicknesses, 100, 300, 500, 700, 1000 and 1200 nm have been prepared on 8" silicon substrate. Nanoindentation tests were performed on these films to study the effect of thickness on the nanomechanical behaviors. Fig.5 shows typical load-displacement curves of the BD thin films (100, 300, 500, 700, 1000 and 1200 nm) using nanoindentation CSM technique. By using this CSM technique, hardness and modulus can be determined as a function of indentation penetration depth with a single nanoindentation load-unload cycle. Berkovich indenter was employed in all experiments and a series of ten indentation tests were performed on each sample. The Poisson's ratio of the BD films of different thicknesses in nanoindentation experiment data is taken as 0.25, because the Poisson's ratio has a negligible effect on the indentation results [41]. During indentation, almost all BD films exhibit pop-in events as indicated by arrows in Fig. 5 due to failures in the films and it is evident from the optical micrographs (Fig. 6) and the corresponding pop-in events are marked on hardness and modulus vs. displacement graphs in Fig. 7. As the thickness increases, the degree of failure or the extent of damage increases in nanoindentation testing and it can be observed from the optical images shown in Fig. 6, where cracks are indicated by arrows on the micrographs. Many researchers have observed this kind of fracture behavior (pop-in event) in various types of low-k materials, bulk glasses and silica foams [42][43][44][45][46] Table 5 gives the information about the BD films fracture/delamination during nanoindentation testing, in terms of threshold load, threshold indentation depth and % of thickness at which film cracking occurs. For 100 nm thick film, failure is observed when the indenter tip is in the substrate and it can be seen in Fig. 5. In case of BD films with thickness 300-1200 nm, failure is observed within the films at different loads and indentation depths as shown in Fig5 and Table 5. It is found that as the BD film thickness increases the threshold load of cracking and the threshold indentation depth increases. One common trend observed in the fracture among BD films (300-1200 nm) is that, the film failure (crack or/and delmaination) occurs at around 60-65% of the film thickness in indentation testing. This data is very useful in conventional nanoindentation processes to determine the physical properties of BD films, i.e. the threshold load for the BD films without cracking, threshold loads in CMP process and to measure the fracture toughness of the BD films.   The hardness and elastic modulus as a function of displacement (indentation depth into the film thickness) of all BD samples are shown in Fig. 7. Results at the initial indentation depths show large fluctuations and high values of hardness and elastic modulus as the tip touches the film surface which might be due to the equipment noise and the inaccuracy of the indenter tip function at very shallow depth of indentation. As the depth of the indentation increases, both the hardness and elastic modulus reaches minima region as a property plateau and then tip starts sensing the effect of silicon substrate which results in higher hardness and elastic modulus. This phenomenon is observed only in the case of soft films on hard substrate. Usually, the initial part of the data is usually discarded in nanoindentation analysis and this kind of problem has been observed by other investigators [47][48]. Here, the averaged hardness and elastic modulus of this minima plateau region is used to define the properties of the films. This phenomenon has been validated by comparing the properties at 1/10 th of the film thickness and properties at the minima property region as shown in Table  6. There are no significant differences observed in between properties of the films at 1/10 th of the thickness and properties from minimum plateau region. Hence in this scenario computing properties from minimum plateau region can be more practicable.    Fig. 7) graphs of all BD films, which corresponds to the pop-in events shown in Fig. 5, resulting from film cracking and/or delamination at the BD film-silicon substrate interface. Significant differences in mechanical properties are observed when the BD film thickness is less than 500 nm (100-500 nm), mainly in the case of elastic modulus. When the BD film thickness is greater than the 500 nm (500-1200 nm) no significant variation in mechanical properties are observed and it can be assumed that these properties are representative of the bulk properties of the BD films.

BD sample thickness (nm)
The minima plateau region for the hardness is considerably large and there is nearly no change with respect to different thicknesses, when compared with elastic modulus plateau region. The minima elastic modulus plateau region decreases as the BD film thickness decreases because the effect of substrate is more on elastic modulus for thinner films. In Fig.  7, it is observed that the sharp increase in modulus from the minima plateau region, mainly due to the effect of substrate, is much more on the elastic modulus than on the hardness of the BD films. This is because the elastic modulus is associated with the elastic deformation during nanoindentation, and in contrast, the hardness response of the material is associated with plastic deformation. Extensive simulation studies show that, the effective elastic modulus of a film experiences greater substrate effect than the hardness value [44]. BD -100 nm film shows significantly higher elastic modulus (E=16.48 GPa) when compared to higher thickness BD films and it is expected due to molecular restructuring in very thin BD films (≤100 nm), since the elastic modulus is an intrinsic material property, which largely depends on interatomic or molecular bonds [49]. Hence the higher elastic modulus of BD-100 nm film is probably expected due to stronger molecular bonding between organic (-CH3) and inorganic (Si-O) constituents.

Effect of diffusion barriers on BD stacks integrity
For this study, four samples have been prepared with Ta and TaN barrier layers and dual stacks also have been prepared as BD/Ta/Si, BD/Ta/BD/Ta/Si, BD/TaN/Si and BD/TaN/BD/TaN/Si. Mechanical properties were assessed by nanoindentation technique. For single dielectric stack, the silicon substrate is first coated with Ta or TaN barrier layer of 25 nm thickness by using self-ionized metal plasma (SIP) technique at room temperature followed by the deposition of BD film of 1000 nm thickness by PECVD (plasma Enhanced Chemical Vapor Deposition) technique. For the deposition of dual dielectric stack this procedure was repeated one more time with BD films and barrier deposition. The application of Ta and TaN barrier layers to BD films improves stiffness in addition to other mechanical properties.
The thickness of single and dual dielectric stacks studied in the present work is 1025 and 2050 nm respectively. Fig. 8 shows the typical load-displacement curves of single and dual dielectric stacks. Both single and dual dielectric stacks show pop-in events. From Fig. 9 optical micrographs of residual nanoindentation impressions of single and double dielectric stacks reveal that massive failure of the films is more prominent in dual dielectric stacks. Dual dielectric stacks demonstrate massive failure which can be observed as more pop-in events in load-displacement curves especially at the interfaces, which are shown as dotted lines in Fig. 8. This can be confirmed by observing the residual nanoindentation marks as shown in Fig. 9. Hence, it is expected that crack formation and/or delamination may occur at the interfaces due to indenter penetration as observed by J. Vitiello [50]. In the current study, stacks having same barrier layer (Ta or TaN) are compared with respect to mechanical properties. Hardness and elastic modulus of single dielectric stacks are in the range of 1.43 to 1.91 GPa and 8.35 to 10.03 GPa respectively. No significant difference is observed in the case of double dielectric stacks. Mechanical properties of both single and dual stacks are given in Table 7.

Mechanical properties of the BD stacks with Ta barrier layer
Hardness and elastic modulus of both single and dual dielectric stack with Ta barrier layer is shown in Fig. 10. High hardness values at the film surface for both stacks are observed mainly due to the inaccuracy of indenter tip functions and surface roughness [47]. Large fluctuations in hardness values throughout the film thickness measurements are observed due to the failure of stacks during the nanoindentation. Substrate effect is more prominent in single dielectric stack when compared with double dielectric stack, this is because the thickness of both the stacks are different and there is difference in the number of interfaces. The hardness and elastic modulus values of single dielectric stack is higher than the values for dual dielectric stack and these properties are consistent throughout the thickness of the stacks as shown in Fig. 10. The averaged minima property plateau is used to define the property of each stack and these values are given in Table 7. Single dielectric stack has hardness of 1.91 GPa and modulus of 10.03 GPa, whereas for dual stack, the values are 1.38 and 7.98 GPa respectively. From Fig 10, sudden deviations in properties are observed mainly due to the film failure during nanoindentation process which corresponds to pop-in events in load-displacement curves as discussed earlier. This mechanical property data of single and dual stacks are very useful in CMP performance, for example, single dielectric stack has slower removal rate when compared to dual stack for the same CMP pressure [51][52]. This is mainly due to the higher hardness value of the single dielectric stack. This mechanical characterization data will be very helpful in deciding the CMP loads as per the dielectric stacks.

Mechanical properties of the BD stacks with TaN barrier layer
The total thickness of these stacks are maintained same as in previous section, i.e. 1025 nm for single dielectric stack and 2050 nm for dual dielectric stack. Hardness and elastic modulus as a function of displacement of these stacks measured using the nanoindentation CSM technique is presented in Fig. 11. Single dielectric stacks have slightly higher mechanical properties when compared with dual dielectric stacks as summarized in table 7.
In both cases, the performance of single dielectric stacks is better than that for the dual dielectric stacks. By comparing the single dielectric stacks, BD/Ta/Si has higher hardness and elastic modulus than for BD/TaN/Si stack (Table 7). Thus barrier layer greatly affects the mechanical properties of the single stack. There is no significant difference observed in the case of BD/Ta/BD/Ta/Si and BD/TaN/BD/TaN/Si dual dielectric stacks. It is anticipated that the lower mechanical properties of dual stacks is mainly due to the presence of residual stresses. Usually, dual stacks have more residual stresses when compared with single dielectric stacks as dual-stacked samples are subjected to more processing steps. Compressive stresses in the stacks result in an increased hardness values but tensile stresses cause a decrease in hardness. Therefore, dual stacks are expected to have more tensile stresses when compared with single dielectric stacks.   Table 7. Summary of mechanical properties of single and double dielectric stacks.

Effect of the wafer thinning/backgrinding on the integrity Low-k stacks
For this study, multilayer low-k stack with fifteen different thin films comprising SiN, USG, Blok (SiC), BD (Black Diamond TM , low-k), has been fabricated as shown in Fig. 12 All thin film samples were prepared on 8" Si(100) wafer in a semiconductor processing clean room of class 1000 environment. Samples fabricated in this study are exclusively designed to study the BD (low-k) integrity in the BEOL interconnects and it resembles the Cu/low-k structure of the three metallizations. So the structure has three BD low-k layers at different levels according to the BEOL (Back End of the Line) interconnect design specifications. The total thickness of the multilayer low-k stack is around 3400 nm. Therefore present study gives an outlook about the response of the low-k test structures during back grinding process. To study the backgrinding/thinning effect on the Low-k stacks, all samples have been subjected to backgrinding process by using the commercial backgrinding system. Empirically backgrinding process involves, first coarse grinding using grit #300, then fine grinding using #2000 followed by dry polishing. A total five set of samples have been prepared for this study as, normal sample (without backgrinding), Back grinded samples of four different thicknesses (BG-500, 300, 150 & 75um).
Failure loads, hardness (H) and elastic modulus (E) normal (no back grinding) and back grinded low-k stacks (BG-500, 300, 150 & 75 μm) are computed by analyzing the nanoindentation load-displacement curves as shown in Fig. 13. From Fig. 13, it is obvious that all stacks have shown pop-in event and this event can be taken as the failure load/fracture strength of the stack. These pop-in events in the nanoindentation curves are resulting from the film cracking and delamination of the stack in the form of blisters [53]. is observed among BG-300, 150, and 75 μm back grinded stacks and all these grinded stacks show higher facture strength/loads than the normal stack and BG-500μm. Accordingly the increase in failure load depends on the degree of the back grinding, but not much difference is observed when the wafers are grinded to 300, 150 and 75 μm. After back grinding, the strength of the low-k stack is enhanced, mainly in terms of nanoindentation load and indentation depth and this increase is understood mainly due to the application of mechanical pressure and thermal stresses during back grinding action. The back grinding pressure or load may improve the adhesion, especially Vander walls forces at the multilayered interfaces and cause the densification of the individual films of the stack. It is being investigated by many researchers in the packaging field that the back grinding processes are deteriorating the die strength, but this is not the same phenomenon with the active side of the chip stack.    values among the back grinded stacks. In case of the elastic modulus, the overall trend is mixed, in which initially back grinded stacks exhibit high values and from 1000 nm depth, BG-150 μm stack follows the trend of normal stack and BG-75 & 300 μm stacks show lower modulus values. The mixed trend of modulus values of all samples is mainly due to the fact that, the elastic modulus is highly sensitive and intrinsic property. Elastic modulus is greatly influenced by layers beneath the testing films and substrate. In the case of hardness, the difference between normal stack and back grinded stacks is very clear when compared with the modulus values. As a whole, back grinded stacks exhibit the higher hardness and elastic modulus values, and this trend is quite clear in the low-k region. This might be due to back grinding loads or pressures influencing the interfaces and causing the densification of the films, especially in the low-k region. Sekhar Et al., have extensively studied the nanoscratch behavior on the backgrinded stacks by analyzing the fracture behavior by critical loads [54].
In this study the fracture or failure strength, hardness and elastic modulus of the normal and grinded stacks are analyzed and compared at overall level as the nanoindentation analysis is very complicated and not well established for the multilayered stacks.

Summary
This chapter presents the systematic mechanical characterization of the BD thin films for BEOL interconnects and 3D IC/packaging applications. For this purpose several thin film systems have been chosen which comprises, Black diamond (SiOC:H), USG (SiO2),SiC, SiN and Ta & TaN thin films which have been prepared by using PECVD technique and sputtering technique respectively. Nanoindentation tests with continuous stiffness measurement (CSM) attachment have been performed on all samples to assess hardness (H) and elastic modulus (E) properties. The CSM attachment is preferable because it provides continuous measurement of the hardness and elastic modulus as a function of indentation depth. In this study several Low-k systems have been prepared and characterized as, mechanical characterization of low-k films with different thicknesses, influence of Ta & TaN barrier layers, and effect of wafer backgrinding/thinning on the complete low-k stack which is similar to actual BEOL with three metallization. In case of the thickness dependence of mechanical properties of BD films, hardness and elastic modulus values obtained of all BD films (100-1200 nm) are in the range of 2.02to 1.66 GPa and 16.48 to 9.27 GPa respectively. Considerable thickness dependence of the properties is observed when thickness is less than 500 nm. To study the effect of barrier layers on low-k stack, single and dual dielectric stacks have been fabricated with Ta and TaN barrier layers. In nanoindentation testing, the performance of single dielectric stacks is better than the dual dielectric stacks is mainly attributed to differences in the number of interfaces, total film thickness and residual stresses.
For the first time the effect of the back grinding process on active side of the low-k chip stack has been studied by using sophisticated nanoindentation technique. It is further investigated by analyzing the fracture or failure strength (pop-in event in nanoindentation), hardness, elastic modulus of the low-k stack for both normal and back grinded samples. After back grinding process, the overall integrity of low-k stack is enhanced and thus the back grinded stacks exhibit higher nanomechanical properties than the normal stacks. This can be attributed mainly to the straightening of the low-k interfaces and densification of the BD (low-k) layers during back grinding processes. Based on the results and their detail analysis it can be said that the thermo-mechanical stresses that applied and/or generated during wafer back grinding processes affect the interfaces and nanomechanical behavior of the lowk stack, in turn enhances the overall integrity of the back grinding stacks.

Author details
Vasarla Nagendra Sekhar Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Science Park II, Singapore