FRACTAL GEOMETRIES IN LATERAL FLUX CAPACITOR DESIGN – EXPERIMENTAL RESULTS

Capacitance density is increased when lateral flux structures are used in CMOS technologies compared to classic parallel-palate capacitors. Lateral-flux capacitors where designed based on three different fractal geometries. Capacitors are designed with and without special MMC metal layer available in some CMOS technologies for capacitor design. For theoretical analysis verification a special ASIC has been designed and fabricated in UMC 0.18um technology. Presented result are obtained by measurement of 5 ICs. Some capacitor structures have much higher capacitance density than classic parallel-plates capacitor without MMC layer. Few presented structures have higher capacitance density than parallel-plate capacitor made with MMC layer. Capacitors have small process parameters spread.


Introduction
While designing an ASIC in CMOS technology the space management is crucial. Designer often must struggle to fit in all components of a circuit in a restricted area of an IC. Increasing an available surface generates a considerable cost of fabrication. Analog, mixed-signals and radio frequency circuit require use components that are very area-consuming such as capacitors [4]. If high value of capacitance is required the capacitor occupies area even several times larger than all digital components. Typical CMOS capacitors are made as two layers of metal. Because of relatively thick interlevel oxide layer between plates those capacitors have low capacitance density. This drawback is more burdensome with technology scaling. While every other component in IC gets smaller the capacitors stay relatively the same, because vertical separation of metal layers does not change much in order to avoid cross-talk effects.
Capacitance density is increased when lateral-flux structures are used in CMOS technologies compared to classic parallelpalate capacitors [2]. A cross section of basic structure of a lateralflux capacitor is presented in figure 1. Metal strips with the same plate number are electrically shorted. This arrangement of plates is much more advantageous with technology scaling. When a new CMOS technology is presented it usually means that smaller element can be designed and circuits are more compact. Lateral spacing between elements, in this case strips of metal creating plates, resulting from design rules are getting smaller, but vertical separation between metal layers and their thickness stay relatively the same. Thus influence of lateral flux on capacitance is growing with each new, smaller technology. Smaller bottom plate of lateral-flux capacitor result in decreased parasitic capacitance between plate and substrate. Additionally some of field lines originating from bottom strips of metal are terminated on neighboring plate instead of on substrate further decreasing parasitic capacitance. Use of lateral-flux structures has proven useful in increasing capacitance density [1,3,6]. In [3] achieved density is even several times bigger than of classic capacitor. Although lateral-flux capacitors have many advantages over classic parallel-plate capacitors they have not replaced them in integrated circuits. In UMC 0.18um CMOS technology, which is the main focus of this paper, a new metal layer was introduced specifically for capacitor design. Layer MMC (Meta to metal Capacitor) is located between last (top) metal layer and second-tolast metal layer. Between MMC layer and lower metal layer there is very thin insulation in form of SiO 2 . This layer of insulation is much thinner than between two layers of metal. MMC layer is top plate of MMC capacitor while second-to-last metal layer is bottom plate. Electrical charge is transferred to MMC layer through top metal and VIA. This approach increases significantly the capacitance density of CMOS capacitors. Unfortunately strict design rules regarding this layer are hindering the use of lateralflux structures. In figure 2 there is presented cross section of lateral-flux structure with use of MMC layer witch marked design rules. Unfortunately publishing exact values of design rules would be a breach of license of the UMC 0.18um technology. Lateral flux is smaller between MMC top plates than metal bottom plated as a result of bigger separation. It is because it is required that MMC layer is enclosed by second to last metal layer by x. The distance between neighboring bottom plates is 0,5x while top plates separation is 5 times bigger. Top-down view of enclosure rule is presented in figure 3. This not only influences lateral-flux but vertical flux as well as area of top plates in lateral-flux capacitors is smaller than area of bottom plates. This paper compares the results of designing fractal lateral flux capacitors with MMC layer and without it.

Fractals and quasi-fractal structures
In order to maximize amount of lateral flux a horizontal border between two plates of capacitor need to be as long as possible. One can achieve that by using some fractals as a template for designing a structure. Fractals are self-similar mathematical patterns. Often they are very complicated and not translatable to CMOS topography. As most of fractals are curve based a quasi-fractals structures needs to be designed for implementation. For this three fractals where chosen. Hilbert curve, Peano Curve and Sierpiński fractal which CMOS designs we presented in [4]. They are all space-filling curves and have infinite length in finite area while their fractal number, describing their complexity, is infinite. In [1] capacitor was designed after Koch curve and in [3] Hilbert curve was used, but no direct comparison with other fractal structures was made.
Fractal lines are used as borders between adjacent plates. 11 capacitors where implemented in ASIC:  Two reference capacitors: one, classic with plates made of two regular metal layers 4 and 5called Reference MIM (Metal Insulation Metal), second one is parallel plate MMC capacitor (Referace MMC). All other capacitors will be compared to these two. Design of MMC capacitor based on fractals with higher complexity number was not possible because of design rules. All capacitors have the same 50x50μm area. Figures 4 to 9 preserve scale. In order to better visualize difference between structures that use and doesn't use MMC layer a view from different perspective are presented in figures 10 and 11. Scale in figures 10 and 11 are not preserved for clarity.

Experimental results
After a fabrication of IC, shown in figure 12, capacitance of all structures was measured using probes in 5 chips from one batch. Root mean square and standard deviation of capacitance density were calculated. Results are shown in Table 1. Reference MMC capacitor has a capacitance density of 0.97fF/µm 2 and is 1.5 times bigger than Reference MIM which is as expected. Employing Sierpiński fractal for design of capacitor has opposite effect to indented. Capacitance density for Sierpiński MMC L, Sierpiński MIM L and Sierpiński MIM H is lower than reference capacitors, in fact, in comparison to rest of the structures Sierpiński capacitors have the lowest capacitance density. Use of structure Peano MIM L also gives poor results. In general MIM with low complexity number have capacitance density raised by little or nothing. Capacitors with high complexity: Hilbert MIM H and Peano MIM H, have higher capacitance than reference capacitor. Especially Hilbert MIM H with its 1.07fF/µm 2 capacitance density deserves special interest. Its parameters exceed even MMC capacitors and almost doubles capacitance of Reference MIM. Which is proof that lateral-flux gain is able to do more than compensate of loss of vertical-flux. Unfortunately fractal MMC capacitors have not much better parameters than parallel-plate MMC capacitor. Gain of 0.05fF/µm 2 for Hilbert MMC L does not justify use of much more complicated structure. Use of a lateral-flux structure decreases area of plates in capacitor, which is more severe with very restrictive design rules in UMC 0.18um CMOS technology. Loss of an area of parallel plates and, as a result, vertical flux is too big for lateral-flux to compensate with high gain.

Summary
Use of lateral flux capacitors which structure is based on Hilbert curve fractal can almost be half a size of typical parallelplate capacitor made from two metals. However, if a dedicated layer for creating capacitors is in the disposition to designer, as it was in UMC 0.18um technology, use of fractal capacitors is much less advantageous. If an ASIC is designed in technology that allows for more effective use of lateral-flux capacitors complexity of structures can be increased. Loss of a plate area would not be as severe and thus capacitance density would be higher which in turn means that capacitors can be made on smaller area.

Acknowledgements
This project is supported by NCN NN515500340.