Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Sung-Gun Song; Seong-Mo Park; Jeong-Gun Lee; Myeong-Hoon Oh

주제분류

...

저널정보

대한전자공학회
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 학술저널
Journal of Semiconductor Technology and Science Vol.15 No.2
2015.4 208 - 222 (15page)

저자정보

Sung-Gun Song (Chonnam National University)
Seong-Mo Park (Chonnam National University)
Jeong-Gun Lee (Hallym University)
Myeong-Hoon Oh (Electronics and Telecommunications Research Institute(ETRI))

이용수
내서재: 0

내서재에 추가
되었습니다. 내서재에서
삭제되었습니다.

초록·키워드

오류제보하기

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

#Synchronization #heterochronous clock domain #avoidance of synchronization failure #prediction of synchronization failure #clock predictor