Pre-route EM Verification for Modern IC Layout Using Greedy Methodology

Srinath Balasubramanian; Balreddy Rajitha

doi:10.5573/JSTS.2020.20.4.405

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대한전자공학회
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 학술저널
Journal of Semiconductor Technology and Science Vol.20 No.4
2020.8 405 - 413 (9page)
DOI : 10.5573/JSTS.2020.20.4.405

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Srinath Balasubramanian (SRM University)
Balreddy Rajitha (SRM University)

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Electromigration (EM) is one of the important parameters to consider in the reliability of ICs. However, only few physical design flows exist to EM avoidance in the pre-CTS stage, and hence early EM avoidance framework is presented to identify the affected interconnects by EM using commercial tools. In this paper, a refinement methodology is developed and presented to reduce the EM violations in the MSV design layout and it is demonstrated that proposed framework helps in reducing EM violations along with optimization of performance. The proposed methodology is integrated inside an existing EDA tool and implemented in IWLS benchmark circuit consisting three voltage islands. Experimental results show that the proposed methodology reduces the EM violation in the multiple supply voltages layout while preserving the routing configurations in early stages of physical design process.

#Electromigration #multiple supply voltage #physical design