A QUAD CMOS GATES CHECKING METHOD

The so-called Fault-Tolerant Systems (FTS) use the structural, temporal, functional, or information redundancy for the achievement of the high reliability. For example, Radiation Hardened by Design (RHBD) Systems are Fault-Tolerant Systems. A Passive FTS, due to a very large structural redundancy (Modular Redundancy), produces faults masking. The Triple Modular Redundancy (TMR) Method has more than 300% redundancy. The Quad Redundancy (QR) Method boasts more than 400% redundancy. The CMOS transistors QR (transistor-level redundancy) is the most effective QR. In this case, no voting element is needed. However, this significantly increases the time delay. In addition, it is necessary to ensure compliance with the Mead-Conway restrictions. QR, in contrast to TMR, raises the problem of checking the redundant structure. The author proposes a QR Checking Method based on a selection of substrates of the CMOS transistors. The power lines of the transistor substrates are separated, which ensures the disconnection of part of the reserve. A simulation confirms the feasibility of the proposed method.


INTRODUCTION
Fault-Tolerant Systems (FTS) [1][2][3] are used in critical areas, for example in space equipment, in nuclear power plants, in medical devices, weapons etc. Passive FTS provide fault-masking by the redundant circuits, for example by Quadding or Tripling [4].Triple Modular Redundancy (TMR), masking one fault [5,6], uses three channels A, B, C and a Majority Voter [7,8].A TMR Reliability Block Diagrams (RBD) is shown in Fig. 1.Let P be the failure-free operation probability of a single channel, -the failure-free operation probability of the Majority Voter (MV).Then the failure-free operation probability of the TMR structure according to the RBD shown in Fig. 1b) is described by the expression (1) An Advanced TMR3 RBD masking one fault [5,6] in the channels and one fault in the Majority Voters, include three MV, is shown in Fig. 2  (3 -2 ) .
TMR MV P P P P    (2) The TMR circuit delay increases by the MV delay as compared to the original circuit.In addition, we need three power sources.Quadrupling, that is, using QR at the transistor level, masking one fault in the transistors A, B, C, D [5,6], does not require a voting device [9,10] (Fig. 3).QR RBD is demonstrated in Fig. 4: Taking into account Weibull distribution [11], we get the failure-free operation probability of CMOS QR for n transistors: where -is the failure rate of one transistor (dimension 1/hour), t -is the operation time, -is the Weibull distribution coefficient.The quadding circuit delay increases more than two times as compared to the original circuit.In the case of masking r-faults, we have the corresponding expressions for the Modular Redundancy (MR) where -is the failure rate of one channel, is the failure rate of the Majority Voter; or for the Quadratic Redundancy (QR): Calculations show a higher efficiency of ( 6) as compared to (5).However, when applying ( 6) one runs into problems with observing the Mead-Conway constraints [12] and testing of the Quad CMOS circuits.At the same time, a TMP testing procedure is simply realized by, for example, switching off the power of one of the channels.The author proposes a method for verifying the Quad CMOS circuits based on controlling the power supply of the transistors substrates.

THE CMOS NOT SIMULATION
Let us consider the simplest CMOS gate, that is, the NOT gate, whose logical function is: The power supply (+) switch function is described by the expression The CMOS NOT Gate flowcharts are seen in Fig. 5.In Fig. 5a), means a p-MOS transistor, while means an n-MOS transistor.A real MOS transistor has the Gate, Drain, Source, and Substrate, see, Figs.5b) and 5c).The CMOS NOT Gate dynamic simulation by the system NI Multisim (National Instruments Electronics Workbench Group) is seen in Fig. 6.In the case of disconnecting substrates, for example, of the p-MOS, we get a fault as shown in Fig. 7.A similar picture is observed the substrate of the second transistor n-MOS is disconnected.

THE QUAD CMOS NOT SIMULATION
Including the quadding redundancy according to Fig. 3a) DNF option, we obtain a QR CMOS NOT model (Fig. 8).The Quad CMOS NOT Gate dynamic simulation is illustrated in Fig. 9.With such a QR the delay is doubled since there are now not one but two transistors in each circuit.Nevertheless, it provides a fault tolerance -if one of any transistors fails either in the upper or the lower parts of the circuit, or even in the upper and lower parts simultaneously: Turn off the substrate of one p-MOS, and we see that the model is workable, as presented in Fig. 10.Similarly, we can verify that the circuit operates unchanged when the substrate of one transistor is turned off at the top and/or the bottom of the circuit, for example: 1 ; 0 ; ; .

AA A A AA A A
However, if we disconnect two substrates at once in one part of the circuits, a failure occurs, the circuit goes into a fault state.A defect Quad CMOS NOT Gate simulation is represented in Fig. 11.We see that in the case of disconnection of two or more substrates, the shape of the waveform changes, which explains the incorrect operation, for example:

FAILURE FREE OPERATION PROBABILITY OF THE QR AND TMR, TMR3
Calculations with the PTC Mathcad [13] show (Fig. 12) that QR wins over a wide range of time, while TMR does not make sense, and TMR3 is worse than QR and better than a non-redundant circuit on a small portion of the time axis, Fig. 12.At the same time, the cost L in the number of the transistors QR is sometimes even smaller than in TMR.For example, let n=8 (2NOR-2AND or 2NANG-2OR gate), then L(TMR)=8*3+12 (Majority Voter)=36; L(TMR3)= 8*3+3*12 (Three Majority Voters)=60; L(QR)=4*8=32.

CONCLUSIONS
Our results show that it is possible to check up the QR gates and pass-transistors circuits by the use of separate power inputs of the transistor's substrate.Testing with disconnection of substrates can be carried out first at the production stage and then connected to all relevant inputs of the power source and during the operation, for example, using relay switching.If the Mead-Conway restriction is satisfied, then the QR is (in some cases, paradoxically) even less costly than the TMR, since in the latter case, Majority Voters are needed.If a CMOS Majority Voter has 12 transistors, one output MOS QR n-transistor gate is "not more expensive" than CMOS TMR gate in case And if m is the number of CMOS circuit outputs, then in case But the decomposition to comply with the Mead-Conway constraints worsens the efficiency of QR, so it is advisable to combine QR and TMR for the optimal design.

Figure 1 -
Figure 1 -TMR Reliability Block Diagrams: a) Conditional TMR Reliability Block Diagram; b) Real TMR Reliability Block Diagrams :

Figure 2 -
Figure 2 -Improved TMR3 RBD with three Majority Voter: a) Conditional TMR3 RBD; b) Real TMR3 RBDTherefore, we get higher reliability according to the formula

Figure 4 -
Figure 4 -QR Reliability Block Diagrams Let be the failure-free operation probability of the single transistor, then the failure-free operation probability of the QR structure , according to the RBD shown in Fig. 4, is calculated by the formula 4 3 4 (1-).

Figure 6 -
Figure 6 -The CMOS NOT Gate dynamic simulation: a) CMOS NOT model; b) NOT normal waveform

Figure 7 -
Figure 7 -A Defect CMOS NOT Gate dynamic simulation: a) CMOS NOT model with disconnecting substrate of the p-MOS; b) NOT defect waveform

Figure 9 -
Figure 9 -The Quad CMOS NOT Gate dynamic simulation: a) Quad CMOS NOT model; b) Quad NOT normal waveform

Figure 10 -
Figure 10 -A defect but workable Quad CMOS NOT Gate dynamic simulation: a) Quad CMOS NOT model with disconnecting substrate of one p-MOS; b) Quad NOT correct waveform

Figure 11 -
Figure 11 -A Defect Quad CMOS NOT Gate dynamic simulation: a) Quad CMOS NOT model with disconnecting substrate of two the p-MOS; b) Quad NOT defect waveform

Figure 12 -
Figure 12 -Failure-free operation probability curves of the n-transistors gate n t e

Figure 13 -
Figure 13 -Separate power supplies for transistor substrates: a) before checking state; b) after successful checking -ready to work .