Modeling of IEEE1588 on OPNET and Analysis of Asymmetric Synchronizing Error in Smart Substation

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Introduction
As the important node of the smart grid, the smart substation based on network communication provides grid application oriented integration data platform, its biggest feature and advantage is information sharing [1][2][3].The synchronization of high precision data is the important premise and basic properties to realize information sharing.Application system such as relay protection, SCA-DA, PMU and so on has a high requirement on the data synchronization which is paid much attention as the core problem of smart substation technology [4][5][6].
At present, the smart substation data synchronization usually adopts IRIG-B, and uses point-to-point link with exclusive fiber optic, sending the unidirectional synchronization signal.This type of flow reliability conflicts with the network information transmission mode of smart substation [7][8].IEEE1588 as precision clock synchronization protocol matches with Intelligent substation network transmission mode based on IEC61850 [9], can share network resources with other packet, and eliminates the timestamp mark error of NTP/SNTP protocol mode and its synchronization is accurate to sub-microsecond, which is becoming the next generation synchronization mode of the smart substation, with good development prospects.
At the same time, with the inherent defect of uncertain network synchronization, synchronized asymmetry error may occur in the synchronization of IEEE1588 because of differences running state and transmission path in the network.
Under the high data synchronization requirements of smart substation, the issue becomes more prominent [10][11][12].At present, due to the lack of quantitative analy -sis tools and methods, the study of IEEE1588 is limited to the field test, the study on the forming mechanism, influence degree and countermeasure of the dissymmetric error is nearly in a gap, which limits its popularization and application [13][14].
This paper develops a IEEE1588 synchronization process modeling of smart substation with a communication simulation software named OPNET Modeler, and analyses the differences of network status and the master-slave clock synchronization signal transmission path quantitatively [15], then studies the influence on IEEE1588 synchronous asymmetry error [16], as also as its correcting method.

Asymmetric Synchronizing Error
IEEE1588 precision clock synchronization protocol was promulgated by the IEEE standard committee in 2002, which is to meet the high-precision requirement of the measurement and control applications in a distributed network of timing synchronization.It's a brand-new attempt to introduce IEEE1588 into power domain that is consistent with smart substation network transmission, and is beneficial to take advantage of information sharing.But as a network synchronization mode, the problem of uncertainty is also prominent which needs to be studied in depth.

IEEE 1588 Protocol and Synchronization Process
1) IEEE 1588 protocol feature IEEE1588 protocol is a distributed network synchronization protocol, and it doesn't need networking singly [17].It can share hardware resources on network, and chooses multiple transmission paths flexibly, also can get the real-time status of other nodes on network.It ensures the reliability of the synchronization system.
Traditional network synchronization time stamp was performed by the software, and the position of time stamp is on application layer, so the message parsing and packaging processing delay constitute a part of synchronization error.As IEEE1588 Protocol time stamps on physical layer exit by hardware using the technology of accessing MAC by Ethernet media, which eliminates part error of time delay, as shown in Figure 1.
2) Synchronization process IEEE1588 synchronization process is shown in Figure 2.  Assuming that the master clock and the slave clock deviation is offset, that is offset = t slave -t master , the slave clock at the local time t 1 sends synchronization request packets to the master clock, the master clock receives synchronization request packets at the local time t 2 .Assuming transmission delay from the slave clock to the master clock is 1  , so The master clock sends synchronization packets to the slave clock at t 3 , and the synchronization packet includes two time scales as t 2 and t 3 .The slave clock receives the synchronization packet at t 4 .If transmission delay from the master clock to the slave clock is 2  , so All t 1 , t 2 , t 3 and t 4 are known quantities in formula ( 1) and ( 2), but offset, 1

 and 2
 are unknown quantities.
Assumes 1  = 2  , so the slave clock can solve and correct the time error offset based on the formula (1), so

The Influences of IEEE1588 Asymmetric Error
The importance assumption of IEEE1588 synchronization is round-trip transmission path symmetry, transmission delay 1  = 2  , since the differences in both network status and transmission path dynamics, transmission delay 1  and 2  generally are not equal, which cannot be deleted directly, so formula (3) should be corrected as: t  is asymmetric error, the influences of IEEE1588 asymmetric error mainly includes: 1) The difference of transmission path Transmission delay  is composed of link transmission delay and switch transmission delay Synchronous packet is stored and forwarded by the switch address analytical table dynamically, as round-trip transmission path may be different when the synchronous packet passes switch and link, link and D switch are not symmetrical generally.The transfer rate of optical fiber link is 2/3 of velocity of light, that is to say the transmission delay of one 1000-meter link is 5μs.A switch packet processing delay is microsecond level, but the synchronous precision requirement of IEEE1588 protocol is sub-microsecond level, so the unequal t  from transmission path cannot be ignored.
2) The difference of network status The communication running state is dynamic, and running state i is closely related to load conditions of network, so the switch processing delay S switch is different under different running state i .As a result, even round-trip transmission path is symmetry, as the network status is different, then transmissio n delay All the people hold the same attitude that the asymmetric error makes IEEE1588 synchronization precision jitter, but the study of asymmetric error stays on qualitative analysis level because of limited to the research methods.Once the synchronous system of smart substation out of step, the protection device may lock, wrong operator miss operate, even more severe is that the secondary system becomes breakdown.So it is necessary to build a synchronous process simulation model of IEEE1588 and quantitative analysis IEEE1588 asymmetric error and then formulate countermeasures.

Synchronous Process Modeling and Asymmetric Error Analysis
IEEE1588 synchronous process model includes masterslave clock model and synchronous network model, and the model reflects several features: IEEE1588 protocol packet processing mechanism, the technique of time stamp on the physical layer exit by hardware, synchronization network made by switch and optical fiber and asymmetric error [18].

IEEE Master-Slave Clock Model
Figure 3 is based on IEEE1588 master-slave clock model, it mainly completes following several functions:

1) Synchronous packet formation
Master-slave clock sending model produces four main synchronous packets according to different trigger conditions, master clock produces a Sync packet per second, then put Sync packet sending time T1 on Follow up, after receiving the request Delay_req from slave clock, put receiving time T4 on response Delay_resp packet.
2) IEEE1588 protocol package and analysis The four main synchronization packets of IEEE1588 are sync, follow up, delay_req and delay_resp, and they have the same format and the same 64Byte long frame with padding bytes, but their time stamps have different information.Use the following up packet model as an example, origin Timestampas master clock sends time T1, and sync interval is synchronous period(usual is 1 second), grandmaster Clock Variance is the change rate of master clock.The data link layer package and analysis packet MAC address, and interface module is general module, completing the protocol analysis and the data packet filling from the data link layer to application layerin IEEE1588.
3) Time stamp marker and read Different from NTP/SNTP traditional synchronization protocol which is marking and reading time stamp on application layer, time node model of IEEE1588 puts time stamp marker function op_pk_stamp(pkptr) and reading function op_pk_stamp_time_getpkptr) on the exit of the data link layer, to realize time stamp marker and read function of clock, and reduce protocol analysis time.

4) Calculation and correction of Master-slave clock offset and asymmetric error
The slave clock uses formula (7) to calculate and correct master-slave clock offset and asymmetric error t  . ( T is master-slave clock's correction value through the calculation of t 1 , t 2 , t 3

2) Different transmission path
From Table 2, when the number of switch increases one more, transmission delay will increase 87.So when configuration of communication network switch change and master-slave clock round-trip transmission path differ one or one more switch, correction of asymmetric error ∆t must exist.
So assumption of master-slave clock round-trip transmission path is equal exists defect, asymmetric error from different network status and transmission path should be a necessary link of synchronous correction.

Asymmetric Error Correction
There are some differences between smart substation communication network and general LAN: 1) the structure of network is simple.Configuration of smart substation secondary system is normative according to voltage level, the number of devices are limited, switches are no more than four in general; 2) Traffic flow is specific.All automatic business such as measurement, protection, test and control and etc. have their corresponding SV/GO-OSE/MMS/Synchronization information flow, and the feature of information flow is specific, little uncertain flow.Specific feature of smart substation communication network makes asymmetric error correction feasible.

Asymmetric Error Correction Method
Assuming at time t, master-slave clock transmission delay is measured by network monitoring device. and 2t  are got from measurement in operation, correction error exists because of measurement.

Asymmetric Error Correction Simulation Analysis
1) Simulation scenario setting Asymmetric error correction simulation model is shown as Figure 5. Master clock transmission path is from switchA to slave clock, while return path is composed of EDCB.
Setting parameters of asymmetric error simulation as Table 3: 2) Analysis of asymmetric error simulation results Results of asymmetric error simulation are shown in Figure 6.Curve1 is uncorrected asymmetric error t  , from 0 to 34 s, range of is 0-0.987t  s  , synchronous error less than 1 s  , from 35s to 100s, with the increasing   To sum up, asymmetric error of master-slave clock link impacts IEEE1588synchronous precision seriously, while the correction method of this paper will reduce the impact of asymmetric error greatly.Relative certainty of smart substation communication network makes the measurement of 1t t   and 2t  feasible, the problem of asymmetric error of network synchronization can be solved effectively by the error correction which is according to this.

Conclusions
This paper develops IEEE1588 synchronous process model, quantitatively analyses asymmetric error from network running status and the difference of master-slave clock transmission path, researches that the correction can supply a new approach and method expecting for actual measurement for the quantitative analysis ofIEEE1588 synchronization process, and develops research thought of IEEE1588 synchronization uncertainly problem.Although IEEE1588 has necessitated solved questions, IEEE1588 adapts to the development trend of smart substation network transmission.To search and improve reliable method of IEEE 1588 synchronization, overcome network uncertainly shortcomings, make full use of network synchronization is the inevitable trend for the synchronization technique of smart substation.

Figure 1 .
Figure 1.Time stamp of network synchronization.

D 1 S  and 2 
are not equal.

Figure 5 .
Figure 5. Synchronization network model in asymmetric error simulation.

Figure 6 .
Figure 6.Results of asymmetric error simulation

Table 3 . Parameters of asymmetric error simulation.
 after correction, even the differ number of master-slave round-trip is 3, it still can meet the precision requirement of 1 s  .