An Analysis of Buck Converter Efficiency in PWM/PFM Mode with Simulink

This technical paper takes a study into efficiency comparison between PWM and PFM control modes in DC-DC buck converters. Matlab Simulink Models are built to facilitate the analysis of various effects on power loss and converting efficiency, including different load conditions, gate switching frequency, setting of voltage and current thresholds, etc. From efficiency vs. load graph, a best switching frequency is found to achieve a good efficiency throughout the wide load range. This simulation point is then compared to theoretical predictions, justifying the effectiveness of computer based simulation. Efficiencies at two different control modes are compared to verify the improvement of PFM scheme.


Buck Converter Background
For a buck converter, by varying the duty cycle of the switch, a desired average voltage output can be achieved. Figure 1 shows a typical buck converter.
A typical synchronous buck circuit using MOSFETs as a switch is shown in Figure 2.
Power Width Modulation (PWM) signal is the most typical control signal applied on a switch in switching DC converters. It is usually a signal with fixed frequency. Inside one period, the signal is high for a specific percentage of the period (duty cycle) and then turns off; one would intuitively predict that the output voltage would  Frequency is directly related to output ripple. N the output voltage ripple assumed to be much smaller than its average value, most of the inductor current ripple must go through the capacitor. The output voltage ripple can be determined by the following equation.
where T sw is the switching period and f sw = 1/T sw . t much hi Normally the switching frequency should be se gher than frequency of other LC components, ranging from 250 kHz to 1.5 MHz with feedback loop's ac characteristics in consideration [1][2][3]. International Rectifier uses 600 kHz for their IR 3840 regulator [6]; National Semiconductor uses 3 MHz fixed frequency for their LM3677 DC converter [4]. For simulation in this study: V in = 3.6 V, V out = 1.8 V, C = 10 uF, L =1 µH. Output ripple =0.014 V (with output voltage being 1.8 V), we can have the switching frequency equal to 894.42 kHz. Further simulation study shows that this is not the optimized frequency to achieve the best conversion efficiency. In the next section it is found that when frequency equals to 1600 kHz the PWM converter achieved the highest efficiency, with a ripple of 0.05 V. So it is a tradeoff between voltage ripples and efficiency in con-clusion. In a DC-DC converter, the losses can two types: load dependent conduction losses and frequency dependent switching losses. The recent work in power loss analysis can be seen in literature [7,8].

PWM Power Loss Analysis
During the continuous con ductor current won't reach down to zero) where the load current is relatively large, the main contribution of power losses are the conduction loss of the on-resistance of high-side (R on_PFET ) and low-side( Ron_NFET ) switches and the series resistance of the inductor and capacitor (R L, R ESR ).
When in operation the upper path and l are turned on and off depending on the duty cycle. Hence, the average resistance for these switches can be expressed as the on resistance multiplied by the duty cycles. The on-resistance in one switching cycle can be written as: OSFET can be written as:

Conduction Loss on Inductors and Capacitors
a Non-ideal inductor has series resistance consuming extr power when passing through current. As mentioned before the average inductor current is also the same as the load current in Steady-state, the conduction loss can then be written as the product of this current squared and the resistance. Industrial experience shows however that current variation of the inductor also contributes to the loss. A more accurate empirical equation of inductive loss is given as follows: where R L is the inductive resistance, I LOAD s the load i current and ∆I inductor is the inductive current variation.
∆I inductor can be derived as: For capacitor, equivalent-series resistance (ESR) is the main cause for power loss. The empirical capacitive loss equation is given as follows 2 ( 3 )

Switching Losses
Switching losses are freq break down into two categories: hard switching loss and soft switching.

Hard Loss (o
Here t off is the time taken for the current to reach down to asitic capacitors at the total zero when ON gate voltage is canceled and V DS goes to high. t on is the time taken for the current to recover when ON gate voltage is applied and V DS goes low again. The losses due to each action are referred to as turn on loss and turn off loss, respectively.

Soft Loss (gate drive loss)
Soft loss is mainly due to the par switching nodes. Since the switch size has to be relatively large to handle the load current with proper onresistance, the capacitance associated with it at the switching node could be quite significant.
The parasitic capacitance at the switching node, C can be express as follows: Thus, the gate driver loss for each stage can be uitiv Under the con mode, the most do erification onverter im-Basic Theory t low load, int ely given by P gate_drive = C total V 2 f s tinuous conduction minate switching loss is due to the hard switching loss, since it is proportional to both current and switching frequency. However, under the light load condition, the most dominated switching loss is due to the gate drive loss since the current is small. Figure 3 shows the PWM controlled buck c plemented in Simulink. Figure 4 shows power loss of this converter. Figure 5 shows the conversion efficiency versus switching frequency.  we need a control scheme with lower switching frequency or conduction current. Note also the minimum frequency is needed to maintain a demanded output ripple. Pulse Frequency Modulation (PFM) scheme is designed to sufficiently decrease the switching frequency and conduction current at light load while maintaining required output voltage ripple [5].

Control Scheme
Unlike PWM where the P gate and N gate is controlled with duty cycle to be on and off, in PFM they are controlled by Thresholds. To be specifically, the thresholds used in PFM control are High Vout Threshold, Low Vout Threshold, Mode Transit Threshold and Inductor Current Peak Limit. Figure 6 shows how this control scheme advances in time axis. PFM scheme is designed for ligh would be drawn below a thresh-During this phase both switches for output power is all from the all losses could have occurred t load so when the load current increases beyond a certain point, the output voltage old, which is shown in the figure as "Mode Transit Threshold". When this happens, the circuit switches back to PWM mode to keep up with the load demand.

PFM Power Loss Analysis
The reason for loss saving in this control mode is mainly due to the "sleep phase". are turned off, the source capacitor charge, saving on switches and the inductor. During the PFM operation, the output is being charged as needed. Thus, the average inductor current and load current would be smaller than the ripple current and the conduction loss would only occur during "pump phase", resulting in less power loss.
The detail equations are omitted in the paper due to space limitation.

PFM Loss Simulink Verification
LM3677 is a DC converter from National Semiconductor using PFM/PWM control mode. In this device output voltage thresholds are set between ~0.2% and ~1.8% above nominal PWM output voltage. In order to compare conversion efficiency under same criteria, The PFM mode also has to set the same output ripple the same as the one in PWM (1.77 V to 1.82 V). Also the typical peak current in PFM mode is:

Loss and Efficiency Comparison
The blue curves dotted with x are PWM mode, red curves dotted with o is PFM mode. It's easily seen that the loss in PFM is much lower than that in PWM mode at light load (10 mA -40 mA), and rapidly increases with the load going high. Figure 8 shows the loss comparison curves with all losses summed up.
The efficiency is measured with load from 10 mA -110 mA as shown in Figure 9.  From the graph we can rovement at light load varies from 0 -30%. Note in PWM the frequency has been fine-tuned at 1600 kHz so the improvement is pretty significant.
Computer based simulation proved the effectiveness of theoretical prediction on conversion power losses. The proposed PFM control scheme is also verified to have a see that the efficiency im-

Conclusions
p significant improvement on conversion efficiency at light load (as high as 30%).