An Automatic Synchronization Method for Distributed Power Electronics System

Currently, the high-speed serial fiber-optic ring net communication is a main method for performing the distributed control network topology and control mode. Because of a network transmission delay inherent in the topology, synchronization between nodes has become a critical issue which needs to be studied. The existing synchronization methods largely depend on the complex communication protocol. Therefore, this paper has proposed a method of automatic measurement and compensation of synchronization delay, and analyzed its operating principle and implementation procedure in detail. The results obtained from the experiments prove the proposed method to be correct, effective and practicable.


Introduction
With the advent of power electronics building blocks (PEBB), the conventional centralized control mode tends to be replaced by the distributed control network topology and control mode in the high-capacity PECS.Currently, the high-speed serial fiber-optic ring net communication is a main method for performing the complex distributed control, lots of references [1][2][3][4][5][6][7][8][9][10] are found to have made an extensive study of the high-speed serial fiber-optic communication network topology.Because of a network transmission delay inherent in the topology, the solution to the synchronization between the nodes of the system has become critical in the high-speed serial fiber-optic ring net topology.
The synchronization method of the high-speed serial fiber-optic ring net communication was analyzed and studied in [2][3][4][5][6][7].A synchronization method based on PES Net fiber-optic ring net communication was analyzed in [2][3][4][5].The synchronization method used for PES Net is based on the communication protocol defined by the user.In the protocol, the delay between the nodes is preset by the user.If there is a change in the delay between the nodes, it is necessary to modify the communication protocol so as to limit the system in applications due to low flexibility.A dual fiber-optic ring net(DRPES Net) proposed in [6,7] helps improve the system's redundancy and reliability.A communication network topology based on the hardware switching data source proposed in [10] can greatly reduce the delay of the whole network, with an error in the delay between the nodes as 60ns, but has not taken into account the effect of the lengths of fiber-optic lines between the nodes on the system's synchronization delay compensation.
This paper has presented a method for the automatic measurement and compensation of the system's synchronization delay.The method can automatically calculate the overall network transmission delay and total number of salve nodes of the system and can according to different lengths of the fiber optical lines used, work out the processing delay of communication data and command through each slave node, thereby compensating for the synchronization delay of each node in the system automatically.

Synchronization of the High-speed Fiber Optic Ring Net Communication Network for the PECS
The topology of the high-power fifteen-phase propulsion converter for marine propulsion is shown as Figure 1.
Each inverter unit and brake unit is regarded as a node.
There are 18 slave nodes altogether, with each node equipped with a slave controller.The whole control network is formed into a ring net with the communication rate of 125 Mbps by a single optical fiber.It can be seen from Figure 1 that the distance between nodes of the system is unequal in the actual laying-out.For the con-verter as shown in Figure 1, the paper proposes a method for automatic measurement and compensation of system synchronization delay.The method can be used to automatically calculate the processing delay of the system data and command passing through each node according to different lengths of the fiber-optic lines between the nodes.
The model for measuring the system delay is shown as Figure 2. The fixed fiber-optic transmission delay t di (i=1, 2, 3, …, n+1) between the nodes is not equal.The structures and chips of each slave node in the system are the same, so that the processing delay of the system data and command passing through each slave node can be considered approximately equal, which is t avg .During the initial period of the system, the master node sends a synchronous sequence frame, whose format is shown as Figure 3(a).The initial value of the node test address is 0. When each slave node receives its node test address, the address will be obtained by adding 1 to this node's address and then retransmitted to the next node.Therefore, the total number of the slave nodes of the whole system will be derived when the node test address returns to the master node.The master node sends a synchronous sequence frame and saves the transmission time t start , and also the reception time t end when it receives the synchronous sequence frame, as shown in Figure 2, it can be derived as: 1 where t total is the total transmission delay of the whole network and n is the number of slave nodes.
According to Figure 2 and equations ( 1)-( 2), the compensation delay of each slave node of the system can be derived as: ( 1) where the t comp(i) (i=1,2,3,…,n)is the preset delay time value of compensation for slave node.The slave node can complete the delay compensation of the system according to the value preset by the compensation timing counter.In the case of the fiber-optic connecting lines between the nodes that are equal in length, equation ( 3) is also available.At this time, t di (i=1,2,3,…,n)are equal.

System Experiments
In order to verify the method for delay automatic measurement proposed in the paper, and an actual ring control network has been established for the purpose of the corresponding experiments.The control ring network used in the experiments on the system is shown as Figure 2, and the n is equal to 3. The adopted formats of data communication frame are shown as Figure 3(a) and Figure 3(b) respectively.A fiber-optic line with 6 meter is used between the master node and the first slave node, 66 meter between the first slave node and the second slave node, 6 meter between the second slave node and the third slave node, and 6 meter between the third slave node and the master node.As the fiber-optic line delay is 5ns/m, t d1 =t d3 =t d4 =30ns and t d2 =330ns.
Figures 4 and 5 respectively show the data communication waveforms of synchronization delay measured from the master node and the slave nodes captured by the signaltap II logic analyzer in quartus II, with 10ns as the minimum scale of time used.
Figure 4 shows that the synchronization test command sent by the master node is "1" and the node test address is "0".Through the whole ring network, the node test address received by the master node turns out to "3", so the total number of the slave nodes of the whole network is "3".Meanwhile, the total network delay of the whole system is "365" obtained from the calculation by the master node.Therefore, the network delay of the whole system is 3650ns.Similarly, the processing delay of the system data and command passing through each node is 810ns.Figure 5(a) indicates that the node test address received by the slave node 1 is "0" and is transmitted as "1".In Figure 5(b), the node test address received by the salve node 2 is "1" and is transmitted as "2".In Figure 5 (c), the node test address received by the slave node 3 is "2" and t is transmitted as "3".From Figures 4 and 5, it is found that the system works normally.
In order to demonstrate the correctness and feasibility of the method proposed in the paper, different lengths of the fiber-optic lines are used between the nodes, as shown in Figure 2. The synchronization experiments without delay compensation, with delay compensation by average value method and with delay compensation by the proposed method in the paper are carried out respectively.The experimental waveforms are shown as from Figures 6(a)-(c).The channels of ch1, ch2 and ch3 represent the synchronization flags of slave node 1, slave node 2 and slave node 3 respectively.Figure 6(a) shows the experimental waveforms without delay compensation.According to the analysis of above, the theoretical delay time value between slave node 1 and slave node 2 is 1.14μs and that between slave node 2 and slave node 3 is 840ns.Figure 6(a) shows the delay time between slave node 1 and slave node 2 is about 1.13μs and that between slave node 2 and slave node 3 is about 840ns, which ba-sically conform to the theoretical values.Figure 6(b) shows the experimental waveforms with delay compensation by average value method.There appears a large error in delay between the generated synchronization flags due to the fiber-optic lines with different length.Figure 6(b) shows the delay between slave node 1 and slave node 2 is about 240ns and that between slave node 2 and slave node 3 is about 70ns. Figure 6(c) shows the experimental waveforms with the proposed method in the paper.The waveforms derived in Figure 6(c) are given delay compensation according to equation (3). Figure 6(c) indicates that the system is well synchronized, with small delay between the generated flags,that is about 33ns between slave node 1 and slave node 2 and about 24ns between slave node 2 and slave node 3.

Conclusions
The existing synchronization methods for fiber optic ring network communication don't take into account the effect of the lengths of fiber optic-lines between the nodes on the system's synchronization delay compensation.For this reason, this paper has proposed a method for the automatic measurement and compensation of synchronization delay based on high-speed fiber-optic ring network communication.Using this method, it is possible to automatically calculate the total network delay and the number of slave nodes of the whole system by using the master node to send a synchronous sequence frame.According to the network delay and the number of slave nodes, it is convenient to calculate the processing delay   time of the system data and command passing through each node by the master node, and then to fulfill the delay compensation by use of the timing counter of FPGA in each slave node, thereby synchronizing the whole system.

Figure 1 .
Figure 1.The topology of the high power fifteen-phase propulsion converter.

Figure 2 .
Figure 2. The model for measuring the system delay.

Figure 3 .
Figure 3. (a) The format of synchronous sequence frame (b) The format of delay data transmitting frame.

Figure 4 .
Figure 4.The communication data of delay automatically measured from the master node.

Figure 5 .
Figure 5.The communication data of delay automatically measured from the slave nodes (1~3).