[1]
|
K. Zhang (Ed.), “Embedded Memories for Nano-Scale VLSIs,” Integrated Circuits and Systems Series, Springer, 2009.
|
[2]
|
International Technology Roadmap for Semiconductors, 2003. http://www.publicitrs.net
|
[3]
|
K. M. Kao, W. C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, “BSIM4 Gate Leakage Model Including Source-Drain Partition,” Proceedings of International Electron Devices Meeting, San Francisco, 10-13 December 2000, pp. 815-818.
doi:10.1109/IEDM.2000.904442
|
[4]
|
L.-J. Zhang, C. Wu, Y.-Q. Ma, J.-B. Zheng and L.-F. Mao, “Leakage Power Reduction Techniques of 55 nm SRAM Cells,” IETE Technical Review, Vol. 28, No. 2, 2011, pp. 135-145. doi:10.4103/0256-4602.78105
|
[5]
|
C.-H. Lo and S.-Y. Huang, “P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 3, 2011, pp. 695-704.
doi:10.1109/JSSC.2010.2102571
|
[6]
|
K. Flautner, N. S. Kim, S. Martin, D. Blaauw and T. Mudge, “Drowsy Caches: Simple Techniques for Reducing Leakage Power,” Proceedings of 29th Annual International Symposium on Computer Architecture, Anchorage, 25-29 May 2002, pp. 148-157.
doi:10.1109/ISCA.2002.1003572
|
[7]
|
C. H. Kim, J.-J. Kim, S. Mukhopadhyay and K. Roy, “A Forward Body-Biased Low-Leakage SRAM Cache: Device, Circuit and Architecture Considerations,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 3, 2005, pp. 349-357.
|
[8]
|
N. Kr. Shukla, R. K. Singh and M. Pattanaik, “A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a Conventional SRAM Bit-Cell Structure at Deep-Sub Micron CMOS Technology,” International Journal of Computer Applications (IJCA), Vol. 23, No. 7, 2011, pp. 23-28.
|
[9]
|
G. Razavipour, A. Afzali-Kusha and M. Pedram, “Design and Analysis of Two Low-Power SRAM Cell Structures,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, 2009, pp. 1551-1555.
|