A NOVEL VOLTAGE-MODE LUT USING CLOCK BOOSTING TECHNIQUE IN STANDARD CMOS

In a VLSI circuit, interconnection plays the dominant role in every part of the circuit nearly 70 percent of the area depends on interconnection, 20 percent on insulation, and remaining 10 percent to devices. The binary logic is limited due to interconnect which occupies a large area on a VLSI chip. In this work, the designs of quaternary-valued logic circuits have been explored over multi-valued logic due to the following reasoning. An approach to mitigate the impact of interconnections is to use multiple-valued logic (MVL) , hence, more information can be carried in each wire, reducing the routing network. Therefore, a single wire carrying a signal with N logic levels can replace [log2N] wires carrying binary signals. Therefore, this results in increasing the maximum operation frequency and also reducing the power consumption. Our new clock boosting method overcomes convectional techniques with simple and efficient CMOS structures.


INTRODUCTION
Power dissipation mainly occurs due leakage current and static power dissipation and has formula P d ∝ CV 2 dd Therefore by reducing the capacitance value we can able to reduce the dissipation.one of the important advantage of quaternary logic is that has the reduced noise margin when compared to the conventional binary logic. More over if we use the current mode we have to face the problem in the fabrication process and has the high power consumptions.

BINARY AND QUATERNARY LOOK-UP TABLES
In General Look-Up Tables (LUT) are basically memories, which implement a logic Function according to their configuration. Configuration values C = (c0….. ci, c k-1 ); are initially stored in the look-up table structure, and once inputs are applied to it, the logic value in the addressed position is assigned to the output.
The capacity of a LUT |C| is given by  (2), where b = 4. In this case, the number of functions that can be represented is everywhere 4.3×10 9 for a QLUT with only two quaternary inputs (k = 2), which is much larger than for the BLUT.The quaternary variable y is capable of representing twice as much information as a binary variable x, we note that the cardinality of |Q| = 2 × |B| in our experiments. In other words, two binary variables with the same inputs can be grouped in order to represent a quaternary variable. Such procedure mainly for reducing both the total number of connections and the number of gates.

QUATERNARY LOGIC AND REFERENCE VOLTAGES LEVEL
This design was implemented using a standard CMOS technology, a single supply voltage and a clock boosting technique to incorporate a 16 to 1 multiplexer and a dual quaternary decoder. One of the most important feature that was taken into account was the area usage since that, in order to perform more complex functions, this circuit needs to be replicated a millions of times in the FPGA.The circuit depicted in the table below has two quaternary inputs, QA and QB, which are then computed by the dual quaternary decoder into the QLUT's binary control signals, B00-B33. The multiplexer 16-to-1 consists of sixteen NMOS switches enhanced with a clock boosting technique. When one of the control signals is high, the corresponding QLUT's line-switch-is activated connecting the corresponding QLUT's quaternary input to the output.
The four voltage levels are represented on table . Assuming a rail-to-rail voltage range and equal noise margins for the four logic levels, three different reference voltage values are required, 1/6VDD, 3/6VDD, and 5/6VDD, to determine a quaternary value.A LUT is an array indexing operator, where the output is mapped by the input, based on the configuration memory. The configuration values are initially stored in the LUT configuration memory, and according to the input, the logic value in the addressed position is assigned to the output.

16-1 MUX
A Multiplexer has many inputs and one output has to be selected. Although, the Use of quaternary logic helps to reduce the number of interconnecting wires, which leads to a compact layout, with reduced routing capacitance. We used the typical value for a binary FPGA (10 pF), since it maintain same number of wires, we can increase the number of functions in FPGA.When compared to binary quaternary implementation of 16-1 multiplexer quaternary had the least number of gates. For the binary implementation nearly 30 transmission gates are used but in case of quaternary only 24 transmission gates are used.

CLOCK BOOSTING TECHNIQUES
Clock boosting techniques is the important technique for reducing the interconnection problems and increase the speed with reduced delays.

Fig.1. Proposed transistor-level schematic
Assuming that the capacitor C is discharged and clk1 is set to logic 1 (VDD), N1 turns on and connects node B to ground, while P1 turns off and ensures a high impedance path between the nodes A and B. Simultaneously, P2 is on and gradually charges the capacitor (and node A) to VDD. When clk1 commutes to a logic 0 (ground), N1 turns off; the inverter ties the capacitor bottom plate to VDD and P2 turns off; node Arises to 2VDD and P1 is turned on connecting node B to 2VDD as wanted.  Table 3: The Q-decoder behavior as a function of the quaternary logic value at the input.

QUATERNARY-TO-BINARY CONVERTER
From the above table it shows the binary output as the function of quaternary input. Here Q0 , Q 1 , Q2, Q3 are the binary values meaning 0 (0V ) or 12 (VDD).and q is the quaternary logic.  The main advantage of this structure compared to previous proposed implementations is that it has standard CMOS structures. The Q-decoder is composed of two comparators CP and CN, and other traditional digital circuits inverters, NANDs and NORs.The CP and CN are self-reference analog comparators shown in Fig. 3. With these structures we are able to detect the four possible voltage levels. In a binary implementation, an inverter may be seen as a comparator where the voltage reference is VDD=2. For our quaternary device, we need three voltage references in order to determine a quaternary value, at 1/6VDD, 3/6VDD and 5/6VDD, as depicted in Figure given below Thus first for design of decoder we need to design the three CP, CI,CN .CI is the inverter with the input 1 to get output 0. We also implemented the complete binary and quaternary look-up tables with the UMC 130nm technology in order to evaluate their performance and power consumption. The development of the binary and quaternary LUTs was performed . Transistor widths were kept to the minimum value in order to have a fair comparison between binary and quaternary versions.

Q-DECODER INPUTS AND OUTPUTS WAVEFORMS
The quaternary structure proposed in this paper outperforms the binary implementation in both power Consumption and propagation delay. These results were obtained through CADENCE Spectra simulation. The propagation delay is simply the largest delay from an input to the output of each LUT.

CONCLUSION
In this paper, we have reported an innovative QLUT design that can be used for multiple valued combinational logic or as a building block in FPGAs. The QLUT internal functionality is implemented using simple standard CMOS structures. This feature is achieved through quaternary-to-binary decoders that quantize the input signals. This decoder is based on voltage-mode self-referenced comparators that allows the use of a standard CMOSTechnology and overcomes previous design drawbacks. Also, a CB technique was used to decrease the switches resistance and increase the operation frequency, while at the same time, achieving low power consumption. Therefore, the presented design is a valid solution to reduce the interconnections impact, without increasing Power consumption or losing performance. Experimental results were performed on an ASIC implementation of a full adder employing the designed QLUT. The obtained results attested the circuit feasibility and its advantages, using a standard CMOS process and its main characteristics (timing and power)