Research Articles

Design of fault-tolerant reversible Vedic multiplier in quantum cellular automata

Authors:

Abstract

In modern computational technologies, a major challenge is the design of devices with smaller size, low power dissipation, and high speed. In order to achieve better optimisation in power dissipation, size and speed, it is necessary to find a technological change. Researchers are trying to find ways and means by introducing many architectural and behavioural changes in the available technologies. One such possible solution is to design digital circuits based on reversible logic and implement them in quantum cellular automata (QCA). In a multiplication process, partial product generation and the addition of partial products are the major factors contributing to the propagation delay. In this paper, Urdhwa Triyakbhyam-based Vedic multiplier using reversible logic is proposed. Vedic multipliers result in faster partial products with less number of steps. Ripple carry adders are used for adding the partial product results to obtain the final product. The multiplier modules are constructed using fault-tolerant reversible KMD gates and hence, the proposed multiplier is a fault-tolerant Vedic multiplier. The designed multiplier is realised in QCA. In the proposed reversible Vedic multiplier, quantum cost is reduced up to 72 %, garbage output is reduced up to 87 %, constant input is reduced up to 87 % and the number of gates are reduced up to 57 % compared to the existing conventional and Vedic multipliers.

 

Keywords:

KMD gatesreversible logicUrdhwa TriyakbhyamVedic multiplication
  • Year: 2019
  • Volume: 47 Issue: 4
  • Page/Article: 371-382
  • DOI: 10.4038/jnsfsr.v47i4.9677
  • Published on 25 Jan 2020
  • Peer Reviewed