Monitoring on Creation and Annihilation of Interface Trap Levels with NO Oxidation, Re-Oxidation and N2 Annealing with Conductance Measurements

Xiang Zhou; Collin W. Hitchcock; Rajendra P. Dahal; Gyanesh Pandey; Jacob Kupernik; I. Bhat; T. Paul Chow

doi:10.4028/www.scientific.net/MSF.1004.595

Paper Titles

Compatibility of POCl₃ Gate Process with the Fabrication of Vertical 4H-SiC MOSFETs
p.565

Wafer-Level near Zero Field Spin Dependent Charge Pumping: Effects of Nitrogen on 4H-SiC MOSFETs
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Low-Energy Muons as a Tool for a Depth-Resolved Analysis of the SiO₂/4H-SiC Interface
p.581

Profiling with Depth Resolution of Sub-nm for SiO₂/ SiC Interface by Dual-Beam TOF-SIMS Combined with Simulation
p.587

Monitoring on Creation and Annihilation of Interface Trap Levels with NO Oxidation, Re-Oxidation and N₂ Annealing with Conductance Measurements
p.595

Photo-Assisted Corona-Charge Characterization of Wide Bandgap Interfaces with Deep Traps Invisible in Standard C-V
p.601

Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of C-V Curves TCAD Simulations
p.608

Gate Capacitance and Conductance-Voltage Characteristics of Vertical 4H-SiC MOSFETs
p.614

Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement
p.620

HomeMaterials Science ForumMaterials Science Forum Vol. 1004Monitoring on Creation and Annihilation of...

Monitoring on Creation and Annihilation of Interface Trap Levels with NO Oxidation, Re-Oxidation and N₂ Annealing with Conductance Measurements

Abstract:

We have determined, using the Conductance-Frequency (G-ω) Technique, the creation and annihilation process of the 3 interface trap levels (OX, OX’ and NI levels) previously reported [1-3] and their possible correlation to inversion electron trapping and mobilities. The measurements were carried out on various 4H-SiC Metal Oxide Semiconductor (MOS) capacitors that have been processed using several gate oxide processes [2,5,6]. Our analysis focus on the correlation of the interface trap levels on the process conditions so as to first understand and then control their formation.

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Periodical:

Materials Science Forum (Volume 1004)

Pages:

595-600

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.1004.595

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Online since:

July 2020

Authors:

Xiang Zhou*, Collin W. Hitchcock, Rajendra P. Dahal, Gyanesh Pandey, Jacob Kupernik, I. Bhat, T. Paul Chow

Keywords:

4H-SiC, Conductance Measurements, Interface Traps, MOS Capacitor, NO Anneal

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References

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