[1]
Xianwei Gao, FPGA Implementation of the SMS4 Block Cipher in the Chinese WAPI Standard. The 2008 International Conference on Embedded Software and Systems Symposia (ICESS2008), pp.104-106, China, (2008).
DOI: 10.1109/icess.symposia.2008.76
Google Scholar
[2]
Xianwei Gao, LUT-based FPGA Implementation of SMS4/AES/Camellia. Fifth IEEE International Symposium on Embedded Computing, pp.73-76, China, (2008).
DOI: 10.1109/sec.2008.43
Google Scholar
[3]
Xianwei Gao, RAM-based Reconfigurable Implementation of the MD6 Hash Function. 2009 International Conferences on Embedded Software and Systems, pp.37-31, China, (2009).
DOI: 10.1109/icess.2009.37
Google Scholar
[4]
Zhang Lei, Wu Wen-Ling, Differential Fault Analysis on SMS4. Chinese Journal of Computers, Sept 2006 vol. 29, pp.1596-1531, (2006).
Google Scholar
[5]
Zhang Yuan-Yang, Area-Efficient IP Core Design Of Block Cipher SMS4, Electrical Technology Application, Jan. 2007, vol. 23, pp.127-29, (2007).
Google Scholar
[6]
Li Da-wei, Zhao Xu-xin, Wu Meng, Pipelined High-Speed Implementation of SMS4. Chinese Journal Of Electron Devices, Apr. 2007, vol. 30, pp.590-92, (2007).
Google Scholar
[7]
Douglas R. Stinson, Cryptography, Theory and Practice. Second Edition, Chapman & Hall/CRC, New York, (2002).
Google Scholar
[8]
M. McLoone, and J. V. McCanny, High Performance Single-Chip FPGA Rijndeal Algorithm Implementations, CHES 2001, pp.68-80, (2001).
DOI: 10.1007/3-540-44709-1_7
Google Scholar
[9]
P. Chodowiec, and K. Gaj, Very Compact FPGA Implementation of the AES Algorithm, CHES 2003, LNCS 2779, pp.319-333, (2003).
DOI: 10.1007/978-3-540-45238-6_26
Google Scholar
[10]
X. Zhang, and K. K. Parhi, High-speed VLSI architectures for the AES algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, Issue 9, pp.957-967, (2004).
DOI: 10.1109/tvlsi.2004.832943
Google Scholar
[11]
K. Stevens, and 0. A. Mohamed, Single-chip FPGA implementation of a pipelined, memory-based AES Rijndael encryption design, Canadian Conference on Electrical and Computer Engineering, pp.1296-1299, (2005).
DOI: 10.1109/ccece.2005.1557214
Google Scholar
[12]
Xiaohui Yang, Zibin Dai, Yuanfeng Liu, and Ting Wang, Researching and implementation of reconfigurable Hash chip based on FPGA, Journal of Systems Engineering and Electronics, Volume 18, Issue 1, 2007, pp.183-187.
DOI: 10.1016/s1004-4132(07)60072-3
Google Scholar
[13]
M. Zeghida, B. Bouallegue, A. Baganne, M. Machhout and R. Tourki, A Reconfigurable Implementation of the New Secure Hash Algorithm, ARES, 2007, p.281–285.
DOI: 10.1109/ares.2007.17
Google Scholar
[14]
R. Glabb, L. Imbert, G. Julien, A. Tisserand, and N. Veyrat-Charvillon, Multi-mode operator for SHA-2 hash functions, journal of systems architecture, 53(2-3), 2007, p.127–138.
DOI: 10.1016/j.sysarc.2006.09.006
Google Scholar
[15]
Yibo Fan, Takeshi Ikenaga, Yukiyasu Tsunoo, and Satoshi Goto, A Low-cost Reconfigurable Architecture for AES Algorithm, Proceedings of word academy of science, Engineering and Technology, Volume 31 Issue 7, 2008, pp.271-274.
Google Scholar
[16]
Jiqiang Lu, Attacking Reduced-Round Versions of the SMS4 Block Cipher in the Chinese WAPI Standard. 9th International Conference on Information and Communications Security, LNCS, vol. 4861, pp.306-318, ZhengZhou China, (2007).
DOI: 10.1007/978-3-540-77048-0_24
Google Scholar
[17]
Office of State Commercial Cryptography Administration, P.R. China, Functionality and Interface Specification of Cryptographic Support Platform for Trusted Computing (in Chinese). http: /www. oscca. gov. cn, (2007).
Google Scholar
[18]
Zheng Xiu-Lin, Jin Li-Na, Research of SMS4's Implementation in DSP. Journal of Beijing Electronic Science and Technology Institute, Dec. 2006, vol. 14, pp.34-37, (2006).
Google Scholar
