Threshold Voltage Adjustment on 4H-SiC MOSFETs Using P-Doped Polysilicon as a Gate Material

To scale digital circuits, symmetric threshold voltages (Vth) for n-type transistors (NMOS) and p-type transistors (PMOS) are important. One step towards this in silicon carbide (SiC) is selecting a p-doped polysilicon (pPolySi). This implementation has been shown in this work with Vth being evaluated by five different methods. Furthermore, operating temperatures up to 500 °C and their impact on Vth were investigated. It has been successfully demonstrated that elevated temperature shifts Vth of both transistor types towards 0 V, whereas changing the gate electrode from n-doped PolySi (nPolySi) to pPolySi shifts Vth of both transistor types to more positive values. Both effects are complementary for the PMOS, reaching Vth below 4 V.


Introduction
High-bandgap materials like SiC, especially with the 4H-SiC polytype as the most mature one [1], can address operation temperatures beyond silicon's (Si) 200 °C limit [2], making them promising for metal-oxide-semiconductor (MOS) transistors which can operate in harsh environments such as high temperature [2,3].
Doped polysilicon (PolySi) is a known gate material for transistors due to its favorable interface to the silicon dioxide (SiO2) gate oxide [4]. Due to the similarity to Si technology, gate stacks of PolySi and SiO2 are also utilized for SiC transistor fabrication. The selected gate material of a transistor has an essential impact on its Vth, which depends on the work function difference between gate and semiconductor material and is, therefore, affected by type and concentration of the corresponding dopants [1]. The work function difference between SiC and PolySi is about 0.9 eV higher with pPolySi compared to nPolySi [5]. The exact value depends on the specific doping concentrations of SiC and PolySi. Consequently, pPolySi increases flat band voltage and thus Vth [4]. NMOS have an increased Vth with pPolySi, whereas PMOS gain an absolute reduction of Vth due to utilizing negative drain and gate voltages.
In summary, utilization of pPolySi for NMOS and PMOS is recommended for more symmetrical Vth. Separately doped PolySi or channel implantation [6,7] are further possible methods to optimize Vth for both transistor types individually. Originating from SiC NMOS power technology, absolute Vth for NMOS is lower than for PMOS partly due to a development lead of NMOS over PMOS. Hence, symmetrical Vth is not yet state of the art for SiC complementary MOS (CMOS). Thus, further research to improve PMOS Vth is essential.
This work targets the reduction of the absolute value of Vth for SiC PMOS transistors, which were analyzed using five different methods. This enables the option to reduce supply voltage (VDD), making thinner gate oxides possible due to lower power loss on electrical field scaling, and more symmetric Vth matching for digital circuits. One example benefitting from this is an inverter [6]. Such change is realized by utilizing pPolySi, similar to the recent work of Hung et al. [7], but focusing on pure boron ions instead of BF2. Additionally, implantation and annealing parameters were varied to further improve pPolySi sheet resistance.

Sample Fabrication
To identify a suitable p-doped gate electrode, unstructured Si wafers with 530 nm to 550 nm undoped amorphous polysilicon on top of a low pressure chemical vapor deposition oxide layer with about 650 nm were processed. Afterwards, different combinations of ion implantation and annealing parameters for the pPolySi fabrication were investigated.
Two reference samples were processed as first and last wafer in the batch to monitor tool stabilities. These references have boron implantation with an energy of 50 keV and a dose of 5•10 15 cm -2 and a subsequent 5 s first annealing step at 1070 °C after 20 s acclimatization at 800 °C. An additional second annealing step at 980 °C for 2 min was performed on all wafers to emulate contact silicidation from the CMOS fabrication process for comparable temperature budgets. Sheet resistance has been monitored across all wafers on 49 data points after both annealing steps. Transistors, schematically depicted in Fig. 1, were fabricated using a 4H-SiC 1 µm double-well CMOS process with 13 mask layers. Device wells and highly doped contact regions were realized via ion implantation and activation annealing [8]. The resulting surface concentration for nplus and pplus is 5•10 19 cm -3 , whereas pwell has about 1•10 17 cm -3 and nwell features roughly 1•10 16 cm -3 .
The two PolySi doping types were split into separate wafers. In-situ nPolySi and undoped amorphous polysilicon were both deposited at 570 °C with applying higher pressure and higher SiH4 concentration during nPolySi deposition. Furthermore, PH3 and Ar were employed in the chamber, while these gases were not present for the undoped amorphous polysilicon. The reference parameters for ion implantation and annealing were applied for pPolySi fabrication.

Results and Discussion
Sentaurus Process from Synopsys TCAD was used to simulate different combinations of ion implantation and annealing parameters for the pPolySi, which were then realized on Si wafers with 500 nm undoped amorphous polysilicon on top of a SiO2 layer. The mean values of the PolySi sheet resistance are listed in Table 1.  A higher implantation dose results in a higher active dopant concentration on the polysilicon surface and thus lower sheet resistance compared to the reference samples. Increasing annealing time or temperature distributes the ions more equally across the whole thickness, as shown in Fig. 2. This is also possible by adapting the energy to shift the peak of the implantation profile deeper into the PolySi layer, from near the surface towards about half of its total thickness. Differences in sheet resistance between simulation and processed wafers could be attributed to varying PolySi thickness, which was up to 10 % higher than targeted. Additionally, the actual heating and cooling process in the annealing chamber were not included in the simulation. Nevertheless, the investigated parameter variations could already successfully reduce the sheet resistance to about 37 Ω/sq, around 14 % lower than the references. Subsequent experiments could combine different parameter variations for further reduction to try to match nPolySi sheet resistance of about 14 Ω/sq. Both PolySi variants show reasonable transfer characteristics in MOS transistors, presented in Fig. 3. The transistors used in this experiment have a similar gate width and length of 20 µm each. Therefore, short and narrow channel effects on threshold voltage can be neglected. At higher VG, the impact of drain and source resistance results in ID saturation. Consequently, the first section of the transfer characteristics should be considered for Vth comparison.
Even at 500 °C, temperature stability is successfully demonstrated using this approach. Increasing temperature shifts the graphs, and thus Vth, towards 0 V. Substituting nPolySi for pPolySi with the reference parameters increases Vth, shifting it to more positive values for both transistor types. However, this increase of Vth for NMOS provides more symmetric Vth values towards low voltage 4H-SiC CMOS technology, which is also a prerequisite for voltage scaling following Moore's law. To calculate Vth for each data set, literature provides numerous different methods based on Si [9]. In this work, five different methods were selected for the evaluation, namely extrapolation in the linear region method (ELR), transconductance extrapolation method in the linear region (GMLE), second-derivative method (SD), ratio method (RM) and extrapolation method in the saturation region (ESR). The resulting Vth values for each graph from Fig. 3 are depicted in Table 2. With ELR, a tangent at the maximum slope of the ID-VG curve is extrapolated to ID = 0 V. Thus, parasitic series resistances and mobility degeneration can cause the linear region to deviate from its ideal form, which will cause shifted Vth. While yielding plausible results for the PMOS, NMOS results seem to be overestimated. Therefore, it is not ideal for the measured devices.
RM eliminates parasitic series resistances and mobility degeneration by utilizing ID/gm 0.5 -VG characteristics, with gm being the transconductance, and extrapolating the linear region to the x-axis intersection for determining Vth. However, for the measured devices, the linear region is not clearly distinguishable due to noise enhanced by dividing the current by the square root of its first derivative.

Engineering Materials: Research and Application Optimization
This causes some results to be significantly wrong, e.g., the PMOS with pPolySi at room temperature. Also, the clear trend of lower Vth at higher temperature is not consistently present, making this method not applicable for the devices. The remaining three methods are the following: GMLE, which extrapolates the tangent on the maximum slope of the gm-VG curve to ID = 0 V, SD, where Vth is the maximum of the derivative of the gm-VG curve, and ESR, where the tangent at the maximum slope of the ID 0.5 -VG curve is extrapolated to the x-axis intersection. All three methods show similar trends, as depicted in Fig. 4. For better comparison, Vth of PMOS, while being negative, is displayed as absolute values.
It is assumed, that the absolute Vth differences between NMOS and PMOS shifts are at least partially attributed to the different SiC doping. The pwell has approximately one order of magnitude higher dopant concentration at the surface compared to the nwell, which impacts the SiC work function. It is evident that Vth is shifted towards 0 V with increasing temperature, consistent with physics. This temperature dependence of Vth results from two of its components, the contact potential difference between substrate and gate electrode and the band bending, being affected by temperature. For equal doping types of substrate and gate, such as NMOS and nPolySi, these effects are working against each other, yielding a negative temperature coefficient. However, when changing the channel doping type to form a PMOS, an addition happens, resulting in a positive coefficient [10].
From the limited number of measured temperatures, this trend seems to decay exponentially with increased temperature for NMOS. For PMOS, the same trend with noticeable lower reduction at the beginning is observed on pPolySi, whereas the nPolySi follows near linear decrease.
SD values are only slightly higher for PMOS, but have, like ELR, noticeably higher results for NMOS, especially at lower temperatures. A possible explanation for this overestimation could be the high sensitivity to measurement error and noise. Interestingly, ESR has very similar results as GMLE despite being an evaluation method in the saturation regime, compared to the other four working in the linear regime. In conclusion, all three methods are applicable for the measured PMOS devices, whereas only GMLE and ESR should be used for the measured NMOS ones. In addition, these two provide results with the highest conformity for both NMOS and PMOS among the methods.
Compared to nPolySi, pPolySi increases Vth for PMOS by roughly 1.05 V ± 0.3 V across all measured temperatures, consistent with the work function difference described in literature [5]. For NMOS, a shift of approximately 0.6 V ± 0.15 V across all measured temperatures is observed. Currently, the reason for the relatively lower Vth shift compared to PMOS is still under investigation.
Further data from additional devices including variations in channel width and length are required to gather more precise statistics. Besides, higher temperature resolution is needed to describe the a) b) changes over the temperature in more detail. For precise comparison, SiC dopant concentration should be comparable for both transistor types. Nevertheless, for digital circuitry, it would be possible to reduce the required VDD with pPolySi by about 1.65 V ± 0.45 V when only taking Vth into account and other conditions are excluded. Additionally, devices like an inverter will benefit by the symmetric matching of Vth using pPolySi.

Summary
To summarize, pPolySi has been integrated into the SiC CMOS technology with optimized parameters regarding reduced sheet resistance being available for future fabrication runs. The intended absolute Vth reduction for pPolySi PMOS and Vth adjustment between NMOS and PMOS with pPolySi gate material has been successfully demonstrated, thus, contributing to the research towards symmetrical Vth on SiC CMOS for digital circuits such as an inverter.
Furthermore, five different evaluation methods for Vth have been compared and their applicability for the processed SiC transistors has been discussed. GMLE and ESR are the recommended choices for both measured MOS types while ELR and SD are also suitable for PMOS but resulting in slightly overestimated values. Finally, high temperature measurements up to 500 °C have been successfully performed for SiC transistors and the Vth shift towards 0 V at higher temperatures has been highlighted.