Increasing Mobility in 4H-SiC MOSFETs with Deposited Oxide by In Situ Nitridation of SiC Surface

. We present the improvement of SiO 2 /4H-SiC interface quality and high field-effect (FE) mobility ( µ FE ) in 4H-SiC MOSFETs. This is achieved by introducing a nitrous oxide (N 2 O) plasma in-situ pre-treatment before gate stack formation using plasma enhanced chemical vapour deposition (PECVD) oxide followed by a post deposition anneal (PDA) in diluted N 2 O for times ranging from 30 to 120 minutes thereby creating an ultra-thin thermally grown SiO 2 layer at the SiO 2 /4H-SiC interface. MOS capacitors with SiO 2 deposited on in-situ pre-treated SiC surfaces had a lower density of interface traps ( D IT ) for all PDA durations, compared with devices having untreated PECVD oxides or control devices with 30 nm thermally grown oxide. After PDA for 90 minutes, a minimum D IT value of 1.2×10 11 cm -2 ·eV -1 was measured. A peak µ FE value reaching 94 cm 2 /(V·s) was measured in n -channel planar MOSFETs fabricated with PECVD oxide on in-situ pre-treated devices, which significantly exceeds a maximum µ FE of 6 cm 2 /(V·s) in control devices.


Introduction
Silicon carbide MOSFETs are considered promising for power electronics applications.They can outperform their silicon (Si) counterparts in terms of efficiency, blocking voltages and maximum operating temperatures [1].SiC MOSFETs with blocking voltages exceeding 15 kV have already been demonstrated [2] and are commercially available with blocking voltages from 650 to 1700 V, a maximum current up to 125 A, and maximum junction temperature up to 175 °C [3].However, they suffer from low electron field-effect mobility (µFE) due to the poor quality of the SiO2/SiC interface and residual carbon clusters in thermally grown oxide [4].
Fig. 1 is a summary of various approaches investigated to improve the SiO2/SiC interface in MOSFETs [5], and references therein.It can be seen that higher measured µFE correlates with a lower measured DIT.POA in N-rich gases is commonly used to reduce DIT but is only partially successful in improving µFE.Higher values of µFE can be obtained using POA in P or B-rich gases but MOSFETs suffer gate instability issues governed by electron trapping.Thin interfacial layers have also been investigated, with reports of high µFE.We have previously demonstrated µFE of 154 cm 2 /Vs by using an ultrathin (0.7 nm) oxide grown at 600 °C for 3 min followed by a 40 nm Al2O3 to complete the gate dielectric [6][7][8].More recently, a range of pretreatments have shown promising results for reducing DIT.For example, Rozen et al. [9], lower DIT by one order of magnitude when EC -E = 0.5 eV (where E is energy below the conduction band edge EC) for devices conditioned with N2 and followed by high-temperature oxide deposition.Fujimoto et al. [10] proposed a method comprising of plasma nitridation, oxide deposition and following PDA in CO2 ambient, achieving a significantly reduced DIT value around 10 11 cm −2 eV −1 .In this study, we investigate the effect of direct nitridation of the SiC surface before PECVD of SiO2, combined with optimisation of the PDA time in N2O.

Experimental
All samples were cleaned in organic solvents followed by Piranha and RCA cleaning procedures.Test MOS capacitors were fabricated on commercial n -(5.54×10 15 cm -3 , 11.3 μm) epitaxial layers grown on a Si face of 4H-SiC wafers (4° off-axis, 0.02 Ω•cm).After oxide layer formation, titanium (Ti), 10 nm thick, covered by 200 nm of silver (Ag) were deposited by e-beam evaporation and patterned by a lift-off procedure to form the top contacts.
The n-channel planar MOSFETs were fabricated on commercial epitaxial layers p + (10 17 cm -3 , 3 µm)/p -(10 16 cm -3 , 1 µm) grown on a Si face of 4H-SiC wafers (4° off-axis, 0.02 Ω•cm).After a standard cleaning procedure, the source and drain regions were created by multi-energy implantation of nitrogen at room temperature into substrates patterned with photoresist.To protect the samples during post-implantation annealing, a graphite capping layer was applied [11].After the protective layer was removed in a Tegal PLASMOD 100 W Tabletop Plasma Reactor at room temperature for 90 minutes, all samples were subjected to another standard cleaning procedure.The source and drain contacts were formed by e-beam evaporation of 5 nm thick Ti and 90 nm thick Ni, followed by annealing in vacuum at 1000 ºC for 3 min.The same gate metallisation Ti(10 nm)/Ag(200 nm) was used for all MOSFET devices.The channel width (W) and length (L) were 100 µm and 2 µm, respectively.
The SiO2/SiC interfaces were formed in three ways: (i) "TO" (thermal oxide, control) devices had 30 nm thick SiO2 layers grown by thermal oxidation in dry oxygen at 1200 °C; (ii) "PECVD+N" devices had 30 nm thick SiO2 layers deposited by PECVD (350 °C, 1000 mTorr, 20 W) followed by PDA (10% N2O / 90% N2 at 1175 °C) for times of 30 to 120 min, causing an ultrathin SiO2 layer to grow underneath the deposited SiO2; (iii) "N+PECVD+N" devices were processed in the same way as PECVD+N devices but were pretreated with additional in-situ nitridation of the SiC surface before the SiO2 deposition.For the in-situ nitridation, 710 sccm of N2O was used at an operating power of 20 W, pressure of 1000 mTorr and a temperature of 350 °C for 3 mins.This was performed immediately prior to SiO2 deposition in the same process chamber without opening to atmosphere.
Post deposition annealing was performed in an open flow reactor with resistive heating.It is well known that N2O being heated to temperatures exceeding 950 °C decomposes into N2, O2, and NO with subsequent reaction between NO and O2 to produce nitrogen dioxide (NO2) [12].This chain of reactions can be easily detected visually when the exhaust gas changes from clear to a brown colour indicating the presence of NO2.PDA in this gas mixture leads to two processes, SiC/SiO2 interface nitridation and SiC thermal oxidation, which both have an effect on interface state density.To estimate the thickness of additional thermal oxide grown at the interface of SiC and deposited SiO2, the SiC oxidation rate in N2O/N2 (40 sccm/360 sccm) gas mixture at 1175 °C and atmospheric pressure was measured and Deal-Grove parameters A and B were determined.Electrical 158 Formation of Solid-State Structures measurements were performed using an Agilent B1500A semiconductor device parameter analyzer.X-ray photoelectron spectroscopy (XPS) was used to prove the nitridation of SiC/SiO2 interface.XPS spectra were collected using a Thermo K-alpha spectrometer using monochromatic Al Kα radiation with a source energy of 1486.68 eV and a photoemission angle θ = 0º.The samples were not subjected to any treatment prior to the measurements.A Shirley-type background was subtracted, and a Gaussian-Lorentzian function was used to fit the spectra.

Results and Discussion
Fig. 2 shows XPS spectra of SiC surface.A narrow N 1s scan in Fig. 2a shows N not visible with standard clean (blue) but is visible after in-situ nitridation.Narrow Si 2p scans are shown after sample cleaning (Fig. 2b) and after in-situ nitridation (Fig. 2c).Spectra are not normalized, and background is subtracted.The most prominent line (blue curve), located at a binding energy of 101 eV corresponds to the silicon bonded to carbon (substrate).The component at 101.7 eV (yellow curve) can be assigned to the Si-O bond as it is clearly distinct in both spectra, while the component peak (green curve) located at 103.3 eV was detected only in the spectra taken after pre-treatment and, hence, can be attributed to the Si-OxNy bonds.These results clearly prove that the in-situ pre-treatment of the SiC surface in N2O plasma leads to additional nitridation of SiC/SiO2 interface in N+PECVD+N samples.Solid State Phenomena Vol.359 Fig. 3 shows the DIT values near to the conduction band edge at EC -E = 0.2 eV measured in n-type MOS capacitors using the high-low method where high and low frequency C-V measurements were performed at 1 MHz and in the quasi-static mode, respectively.[13], and data points represent the average of measurements from five MOS capacitors.Both PECVD+N and N+PECVD+N devices were subjected to PDA at 1175 °C for 30, 60, 90 or 120 minutes.All devices subjected to the N2O pre-treatment have noticeably lower DIT values for all PDA durations.The N+PECVD+N devices with PDA for 90 min demonstrated the lowest DIT value of 1.2 × 10 11 cm -2 •eV -1 .This result is similar to previous results we obtained, using a 600 °C oxidation to obtain a 0.7 nm thermally grown oxide [6].The optimum DIT was obtained by achieving SiC surface coverage with thermally grown SiO2.A shorter anneal time would yield incomplete SiC surface coverage with thermally grown SiO2 and thereby a higher defect density, while a longer anneal time would yield excess SiC oxidation and thereby increase the concentration of C related defects.While it is difficult to distinguish between a thermally grown thin SiO2 layer and a PECVD deposited SiO2 layer, the same hypothesis can hold here.However, the PECVD deposited SiO2 layer reduces the SiC oxidation rate at the higher PDA temperatures used because oxidation of SiC requires transport of oxidising species through the deposited layer, as described by the Deal-Grove model [12].Having fitted the Deal-Grove parameters A and B to our oxidation furnace data, we can predict that a 1.2 nm SiO2 interfacial layer is grown following a 90 min PDA at 1175°C, where DIT is minimum.This thickness is similar to the measured SiO2 layer of 0.7 nm in our earlier work but needs further investigation in view of the possible impact from the pre-treated with additional in-situ nitridation of the SiC surface before the SiO2 deposition.Fig. 5 shows the impact of the N2O plasma on the SiC MOSFET ID-VGS and ID-VDS characteristics.Devices with N+PECVD+N oxide have higher on-current, which is correlated with the reduced interface trap density seen in Fig. 3 and Fig. 4. Fig. 5a shows there is a shift in threshold voltage (VT), corresponding to a reduction in negative gate charge and therefore less positive gate voltage needs to be applied to create an inversion layer.This reduction in charge is consistent with the reduction in VT instability using the additional in-situ nitridation of the SiC surface before the SiO2 deposition for N+PECVD+N MOSFETs.This is further confirmed by the increased steepness of the subthreshold FE mobility can be calculated from MOSFET electrical measurements by [13]: where    is the intrinsic transconductance, VDS is the source-drain voltage and Cox is measured using a split C-V configuration.High electron mobility is obtained for SiC MOSFETs fabricated with the N+PECVD+N process.This is illustrated in Fig. 6 where the peak µFE value increases from only 6 cm 2 /(V•s) for TO devices, to 20 cm 2 /(V•s) for PECVD+N devices and 94 cm 2 /(V•s) for N+PECVD+N devices.

Summary and Conclusions
This work reports on SiO2/SiC interface quality improvements by introducing a N2O plasma insitu pre-treatment before the oxide deposition and oxidation anneal.It also shows how the improved interface translates to significantly improved MOSFET performance.The N+PECVD+N devices with PDA for 90 min demonstrated the lowest DIT value of 1.2 × 10 11 cm -2 •eV -1 .This results in a maximum µFE of 94 cm 2 /(V•s), together with reduced VT instability and a steeper sub-threshold slope compared with other devices fabricated with differences in gate stack formation.The results give additional evidence of the beneficial role played by an ultra-thin SiO2 layer grown on SiC.Previously this was obtained by annealing at 600 C and here a similar result is obtained at 1175 C when a deposited PECVD oxide is used prior to thermal oxidation.The impact of N2O pre-treatment plays a crucial but complementary role in ensuring high performance SiC MOSFETs.

Fig. 1 .
Fig. 1.Field effect mobility (µFE) as a function of density of interface traps (DIT) at 0.2 eV below the conduction band edge.

Fig. 3 .
Fig. 3. DIT at EC -E = 0.2 eV for n-type MOS capacitors with (N+PECVD+N) and without (PECVD+N) in-situ nitridation of SiC surface pre-treatment followed by oxide deposition and PDA for different annealing times.PDA for 90 minutes gives lowest DIT value.

Fig. 4 .
Fig. 4. DIT near the conduction band edge EC -E for n-type MOS capacitors having a deposited oxide, with (N+PECVD+N) and without (PECVD+N) pre-treatment.Both were subjected to PDA for 90 minutes and show reduced DIT compared with thermal oxide TO control devices.

Fig. 2 .
Fig. 2. XPS spectra taken from the surface of 4H-SiC samples (a) narrow N 1s scan shows N not visible with standard clean (blue) but is visible after in-situ nitridation (red), b) narrow Si 2p shows initial cleaning, and (c) in-situ nitridation of the SiC surface in N2O plasma.Squares represent measured intensities, blue, yellow and green lines represent Si-C, Si-O and Si-OxNy components, respectively.Red line is the components envelop.

Fig. 4
Fig. 4 shows the distribution of DIT near the conduction band edge for the TO, PECVD+N, and N+PECVD+N devices.Our results indicate DIT reducing by about one order of magnitude in N+PECVD+N devices compared with PECVD+N devices and about two orders of magnitude compared with the control TO devices.

Fig. 5 .
Fig. 5. (a) ID vs VGS transfer characteristics measured at drain-source voltage of VDS = 0.1V and (b) ID-VDS output characteristics measured up to a gate overdrive, VGS-VT, of 5 V for n-channel 4H-SiC MOSFETs having gate stacks corresponding with the three fabrication options resulting in DIT as shown in Fig. 4.
slope, which depends on interface trap density[6].Fig.5bshows the family of curves for ID-VDS in the case of N+PECVD+N MOSFETs up to a gate overdrive, VGS-VT, of 5 V.The ID-VDS result is showing that they behave well and have good electrostatic control.For clarity the much smaller current achieved in the other devices is shown only for the maximum gate overdrive (5 V).
AcknowledgementM.Y. appreciates the financial support of the Republic of Türkiye Ministry of National Education.