Improvement of Interface Properties for Thermally Oxidized SiC/SiO2 MOS Capacitor by Post Oxidation Annealing Treatment

In this work, we report an innovative approach to improve the interface properties of SiC/SiO2 metal oxide semiconductor (MOS) capacitors. High temperature (1350°C) oxidation under different ambient is followed by a combination of post-oxidation annealing (POA) treatments using N2, N2O and NO gases. TOF-SIMS analysis shows silicon and nitrogen peaks near the SiC/SiO2 interface. The silicon peak is attributed to the emission of silicon and carbon atoms during high temperature oxidation. The accumulation of nitrogen is caused by the presence of nitrogen during oxidation or POA. One of the lowest interface-trap densities along with good dielectric strength has been demonstrated with the N2 and NO gas POA treatment.


Introduction
Silicon Carbide (SiC), in particular 4H-SiC polytype, is one of the most promising semiconductor materials for high-power devices due to its' wide bandgap, high breakdown electric field, and large thermal conductivity [1,2]. Although SiC MOSFETs are commercially available, the on-resistance of medium voltage class SiC MOSFETs (∼1 kV) is much higher than expected from the physical properties of bulk SiC due to the low channel mobility. This is attributable to the high interface state density (Dit) in SiC/SiO2 structure [3][4][5]. Although, the exact origin of the high Dit for SiC/SiO2 structure has not yet been identified, it is widely considered that carbon atoms that remain at the interface are plausible candidates. The key to obtain a high-quality SiC/SiO2 interface may be the formation of SiO2 on SiC without the creation of carbon-related defects and crystalline disorder [6].
To enhance the performance of SiC devices further for enabling applications in high-power and high-performance electronics, the improvement in mobility is very critical. To achieve that, a reduction of Dit is strongly required. Post-oxidation annealing (POA) is widely used as a passivation method [7,8] to improve channel mobility to some extent without substantial degradation of the dielectric properties of the gate oxide. However, till date, there are very few reports on the physical and chemical effects of the oxidation and annealing ambient on SiC/SiO2 interface properties and channel mobility of SiC MOSFET.
In this work, we report on the engineering of the SiC/SiO2 interface using different oxidation and post oxidation annealing (POA) treatments to improve the SiC/SiO2 MOS interface. C-V results show that the interface trap density (Dit) was significantly reduced to 3×10 10 /eV -1 cm -2 .

Results and Discussion
The SiC/SiO2 MOS capacitors were fabricated on a 4⁰ off-cut (0001) Si-face of 4H-SiC with a 10µm thick N-doped homo-epilayer deposited on a highly doped n-type substrate. The key process flow is described in Fig.1. Pre-gate surface cleaning was performed via RCA method followed by diluted hydrofluoric acid (DHF) dip. SiO2 layers with a thickness of 50 nm were grown via thermal oxidation at 1350 o C in O2 for 18 minutes, followed by post-oxidation annealing at 1300 o C in N2, N2O and NO gas for 30 min. The detailed thermal oxidation conditions are described in Fig.1. After each oxidation, the grown oxides were characterized by cross-sectional transmission electron microscopy (TEM) and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) measurements. A 200 nm thick aluminum metal was evaporated on the front side using a shadow mask to create top electrode of the MOS capacitor while blanket metal was deposited on the back surface of substrate to form back contact. In the following electrical characterizations of the devices, a B1500A semiconductor parameter analyzer is used. To confirm the influence of annealing on SiC/SiO2 interface, ToF-SIMS data of the SiO2 layer is analyzed (Fig.2). The devices treated with N2 and NO gas shows the presence of nitrogen at the SiO2 interface as observed on the peak location inside the SiO2, implying that annealing process only affects the interface and not the physical morphology. Si peak was also observed at the interface due to the migration of Si and C during the thermal oxidation process [11]. The migrated C interstitials into the oxide diffused toward the oxide surface, which react with O2 to form CO2 and evaporated. Fairly Si-rich interfacial layer exists at high-temperature oxidation process as observed from TOF-SIMS.

Silicon Carbide MOSFETs and Special Materials
Moreover, we have carried out high resolution cross-sectional TEM imaging of our samples to examine the existence of any other additional layer at SiC/SiO2 interface after POA treatment as shown in Fig. 3. Observation of no additional layer implies that the POA treatment process only affects the gate dielectric and interface trap charges, and not the physical morphology. The nitrogen profiling was carried out using EDX of HRTEM as shown in Fig.4. Nitrogen rich layer thickness in SiC near SiO2/SiC interface clearly observed. Gate leakage current density (JG) is plotted as a function of VG as shown in Fig. 5(a), to examine the film quality of the SiO2 gate dielectric. The extrapolated gate leakage current density (JG) is 10 -10 A/cm 2 in the range of the applied VG from 0V to 25V for 50nm SiO2 and this suggests superior film quality of the SiO2 gate dielectric.
Furthermore, a capacitance-voltage (C-V) test under forward and reverse sweep of gate bias is performed to further investigate the effect of POA at the SiC/SiO2 interface. Fig. 5(b) shows the measured C-V characteristics of all the fabricated SiC/SiO2 MOS capacitors at a high frequency of 1MHz. It is found that the device with SiO2 treated by N2 and NO POA exhibits the smallest clockwise hysteresis. Such small hysteresis window indicates that the presence of least number of traps at the SiC/SiO2 interface. The interface state density is extracted using Hill-the Coleman conductance method [2]  where Gm, max and Cm are the corresponding peak conductance capacitance respectively at the same gate bias, Cox is oxide capacitance at accumulation, obtained using single frequency Cox-VG techniques. Fig. 5(d) benchmarks the Dit of SiC/SiO2 MOS capacitors and other reported SiC based MOS capacitors [9,10]. It is clear that the device with N2 gas POA+NO gas POA treatment in this work achieves lowest Dit (3×10 10 /eV -1 c m -2 ) among all SiC-based capacitors. However, DoE-2 resulted in the highest density of net positive charge in SiO2 film. These 4 DoE results suggested that channel mobility, Vth and JG leakage can be trade-off and optimized to meet a wide range of applications using SiC-based devices.

Summary
In summary, we have presented the effect of high temperature oxidation and post oxidation annealing on the SiC/SiO2 MOS capacitors. Interestingly, it is found that the SiC/SiO2 interface are effectively influenced by POA treatment on the SiO2 layer. It is noticed that N2 gas POA+NO gas POA treatment improves the SiC/SiO2 interface quality. The lowest Dit, almost hysteresis-free, and decent gate leakage current density among other post-oxidation annealing conditions have been experimentally demonstrated.