Investigation on Switching Characteristics of 3.3kV SiC Power MOSFETs with SiO2/ SiN Gate Stack

This paper focuses on reporting the switching behaviour of our Silicon Carbide (SiC) power MOSFETs, rated 3.3kV – 25A. The devices are based on a gate stack formed by SiO2/SiN and have been tested during Inductive Load Switching (ILS) in different conditions (nominal and SOA) with different chip configurations (single/multiple dies). In this contribution, the turn–on and turn–off curves are reported, along with the extracted RBSOA and switching energies.


Introduction
Silicon Carbide (SiC) power MOSFETs are nowadays established components in a wide range of power systems, thanks to the well-known advantages they bring compared to Silicon devices. Although the main drivers for SiC power markets are low voltage devices (900V-1.7kV), the use of 3.3kV-rated SiC power MOSFETs for medium voltage (MV) and high voltage (HV) applications (e.g. high-speed rail traction) has recently become more and more attractive [1]- [2] . One of the main factors to improve the overall performances of SiC power MOSFETs is reducing the channel resistance contribution. If on one hand this is achievable by increasing the channel density (e.g. reducing the pitch size), most of the focus in the past years has been dedicated to improve the SiC/gate-dielectric interface's quality. While high-k materials have been researched before as potential gate dielectrics in SiC technology [3]- [4], we have been the first to prove the benefits brought by the integration of high-k gate dielectrics in fully operational power SiC MOSFETs [5]- [7]. The main benefit of using such gate structure is a reduced interface state density (Dit), corresponding to a higher channel electron mobility and an improved threshold voltage (VTH) stability.
In this work we report the dynamic behaviour of our 3.3kV SiC MOSFETs fabricated using a SiO2/SiN gate dielectric stack technology.

Gate Technology
As mentioned before, implementing a gate dielectric based on high-k material brings along several advantages [5]- [7]. The immediate effect of a gate layer with higher dielectric constant εD is the larger dielectric capacitance CD (for a given dielectric thickness tD). This implies an increased channel carrier concentration nS that enhances the conduction current, i.e. reducing the channel resistance. Additionally, we have also demonstrated [5] that, given an adequate process integration scheme, a high-k material considerably reduces the interface Dit. The first consequence of having less defects states across the semiconductor/gate interface is to lower scattering effects, resulting in an increased inversion channel mobility. Moreover, a significant reduction of the traps leads to a much more stable threshold voltage [6].
We have successfully applied our first generation of high-k gate to 3.3kV devices, showing their rugged dynamic behaviour in [8].  On the other hand, the focus of this contribution is on the switching behaviour of our HV devices fabricated with a gate stack composed of very thin layer of standard oxide with a layer having higher dielectric constant above it. The resulting SiO2/SiN gate structure is sketched in Fig. 1(a). The purpose of this choice, compared to our previous high-k technology, is to investigate the behaviour of the device when only higher gate dielectric capacitance is used, without benefiting from the improved and higher mobility.
In such a structure, it is easy to evaluate the whole dielectric capacitance as the series connection of the two capacitances corresponding to each of the two stacked insulating layers: It can then be approximated to the capacitance of the layer with higher dielectric permittivity when the SiO2 layer is much thinner than the one on top (1). Fig. 1(b) depicts the dependence of the total dielectric capacitance for different oxide layer thickness. Predictably, the thinner the SiO2 becomes, the closer the whole capacitance value is to the pure SiN case.
The electric field in the semiconductor, for a given applied gate voltage VG, could also be derived using Gauss' Law and considering the effect of the SiO2 interlayer: That can be manipulated as: The equation can be read as the equivalent of the field in the semiconductor as if no buffer was present E ′ SiC, multiplied by a scaling factor S dependent on the layers' capacitances. It is easy to understand through (1)-(3) that the SiO2 layer behaves as a buffer layer and can be designed to modulate the input capacitance and the surface electric field in the semiconductor by varying the thickness tOX.

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Technologies and Application of Engineering Materials

Dynamic Characterization
Devices were assembled on substrates in different configurations, namely with single and up to 4× parallel chips and investigated during standard Inductive Load Switching (ILS) test.
As first step, the devices have been tested in nominal conditions, meaning VN = 1.8kV and IN = 25A/device; for all the tests the temperature has been set to T = 150°C and the double-pulse tester had a fixed stray inductance of L σ~9 0-100nH. Similar to what was shown for a high-k gate in [8], also the proposed SiO2/SiN bilayer allows to drive the gate with voltage swings wider than commercially available devices. In all the results reported here, a Si-like driving voltage of VGS = ±15V was used.
The turn-off waveforms in case of single and four devices in parallel are reported in Fig. 2. For this analysis, the gate resistor and the stray inductance were not scaled for parallel devices, implying that the RG/chip and L σ /chip are higher for the substrates with four MOSFETs. This is reflected for example in the larger overshoot for the drain voltage in Fig. 2(b) due to the higher parasitic inductance. Also, the expected influence of the gate resistor on the switching speed dVDS⁄dt is clearly spottable. The more pronounced oscillations on the current waveforms are not chip-related, produced by the experimental setup itself.
The MOSFETs' voltage and current limitations were then explored by gradually increasing the test current and voltage values, reaching twice the nominal current and a voltage of 2.6kV. The respective turn-off waveforms with ID ranging from IN to 2×IN are plotted in Fig. 3(a-b). From the mentioned curves it is also possible to extract the corresponding Safe Operating Areas (SOA) as depicted in Fig. 3(c). It is worth to mention that the substrates with parallel chips still display rather clean waveforms and reasonable voltage oscillations, despite the fact that both voltage and current are beyond nominal values. That proves a balanced current sharing between devices given by an engineered substrate design oriented to the minimization of parasitic components. For a more comprehensive investigation, the switching behaviour of MOSFETs with the proposed SiO2/SiN structure has been compared to devices with same design but fabricated with our standard SiO2 gate dielectric. In Fig. 4(a), the total switching energy EON + EOFF per chip, calculated in nominal conditions (VN = 1.8kV, IN = 25A), is reported for different values of RG. As could be expected, the SiO2/SiN-based devices exhibit marginally higher energy losses due to the increased input capacitance. Nevertheless, the increase in energy for the considered case is still moderately small (~12% max) and, if needed, could be reduced with lower gate resistor values. As already stated, it is in principle possible to modify the dielectric capacitance by adjusting the bilayer design, following a trade-off between conduction performances and switching losses. Also, the turn-on and turn-off voltage transients are virtually the same for both dielectric combinations as per Fig. 4(b) for the case of RG = 33Ω.
At last, the dynamic transfer characteristics IDVGS were extracted from turn-on gate voltage and drain current waveforms for both families of fabricated devices at different values of VGS,OFF, and the resulting curves are plotted in Fig. 5. The standard SiO2 shows appearance of dynamic hysteresis as a more negative gate off-voltage is used, while the proposed stack already improves this aspect.

Conclusion
This work has described the dynamic behaviour of our 3.3kV SiC power MOSFETs fabricated with a SiO2/SiN bilayer gate structure. Such devices have been characterized with typical double pulse tests, considering both single and parallel devices operations. The nominal (VN = 1.8kV, IN = 25A/die) and RBSOA (VSOA = 2.6kV, ISOA = 50A/die) operations have been proven for different gate resistors. The switching energies were afterwards compared with standard gate oxide, demonstrating that the increased input capacitance given by the higher dielectric constant, could have limited effect on the dynamic losses.