Study of the Bias Driven T hreshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests

. Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.


Introduction
Although SiC MOSFETs successfully entered the market of semiconductor power devices, there are still aspects related to reliability and robustness which must be addressed.One of those topics is the threshold voltage instability [1], resulting from a wider band gap of SiC compared to Si and a high density of trap states at the SiC/SiO 2 interface (D it ).Both aspects lead to phenomena such as more pronounced bias-temperature instability (BTI) and threshold voltage hysteresis (V GS(T h)Hyst ) [2].Whereas the V GS(T h) -hysteresis itself is referred to be harmless [3] for the switching behavior and the application, the BTI might have a significant impact on the on-state resistance (R DS(on) ) especially for lower voltage class devices.
The BTI-driven threshold voltage drift can be addressed with a high temperature gate bias (HTGB) test.During a power cycling test (PCT) a longer lasting positive and/or negative gate voltage with application levels is applied to the device -similar as for a HTGB.Depending on the selected test procedure in the PCT, either a constant negative gate bias or a very low frequency AC gate voltage can be applied to the specimens [4].A typical end-of-life (EOL) criterion in power cycling tests is an increase of the forward voltage drop by more than 5 %, which might be affected by a potential V GS(T h) -drift during the test.Hence, the lifetime in PCTs might be distorted by this drift.

Test Procedure and Specimens
To analyze the V GS(T h) -drift during the power cycling test, a standard setup has been modified, to enable an in situ threshold voltage measurement, without removing specimens from the test bench.The PCT setup for one single specimen is shown in Fig. 1 together with the read-out procedure for the virtual junction temperature (T vj ) and the threshold voltage according to the hysteresis method in alignment to the JEDEC standard JEP 184 and [2].A detailed description of the setup can be found in [5].Commercially available off-the-shelf 1.2 kV SiC MOSFETs in TO-247-3 package from two manufacturers have been tested under similar test conditions, which are summarized in Table 1.The rated on-state resistance R DS(on) is 75 mΩ for the devices with a planar gate structure (PGM group)  and 80 mΩ for the trench MOSFETs (TGM group), which enables comparable test conditions in the power cycling test.Both groups contained 15 specimens.MOSFET-mode [9] is the recommended procedure for power cycling tests on SiC MOSFETs.Devices under test switch between on-state (t on ) where a DC load current I Load is driven through the specimens and off-state (t of f ) where T vj is being measured at low sense current.During the on-state, a high positive V GS is being applied across the devices under test whereas a negative gate voltage is required in the off-state to apply the V SD (T )-method [4,10].To ensure a precise T vj calculation, the MOS-channel must be suppressed completely with a sufficiently low negative gate bias.For some manufacturers this can be even below V GS = −10 V [12] exceeding the data sheet limits.Although there is a sufficient gap to the dielectric breakdown, the low negative gate voltage will have a significant impact on the interface states [7], the V GS(T h) -drift due to the BTI effect and might have a significant influence on the R DS(on) , which is an important EOL-criterion in power cycling tests.Separated from each other, both gate bias polarities can provoke the BTI effect in different directions but they might result in a superimposed drift after the PCT, containing a share of positive (PBTI) and negative BTI (NBTI).Due to low number of switching cycles, the AC-driven V GS(T h) -drift [6] was not considered.In parallel to the power cycling tests, three gate stress tests with positive, negative, and periodically alternating stress voltage have been performed, including an in situ V GS(T h) read-out according to the triple sense method in alignment to the JEDEC standard JEP 184 and [2], with the intention to predict the V GS(T h) -drift and to separate BTI effects from thermomechanical wear induced V DS -drift

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Solid-State Power Devices: Operational Reliability and Parameters' Stability in PCTs.In every HTGB test 6 pristine specimens for each manufacturer have been stressed at high case temperature (T C = 150 • C) under DC gate bias.To ensure comparability between power cycling and gate stress tests, the same gate voltage levels have been selected as in the PCT, including V GS = 20 V for the PBTI and V GS = −10 V for the NBTI test.V GS(T h) has been recorded in situ with a logarithmically increasing time intervals for a total stress time of t stress = 500 h at high temperature to avoid recovery effects during cooling phases [7].In the third HTGB test (Alt-BTI) the stress bias has been alternated periodically between positive and negative gate voltage to investigate the interaction of PBTI and NBTI effects on the same devices under test.Therefore, the gate voltage has not been switched with an AC signal but basing on a logarithmically increasing stress time, containing a V GS(T h) read-out after every stress period.The total test time was set to t stress = 1000 h containing 500 h PBTI and 500 h NBTI stress.With this procedure it was possible to investigate potential recovery effects, which are related to the opposite gate bias and compare the results of the separated PBTI and NBTI portions with the continuous DC tests.For a reasonable comparison of the test results the threshold voltage drift (∆V GS(T h) ) was fit with a power law according to Eq. 1: with the scale factor A 0 , the power law exponent b and the test time t test .

Threshold Voltage Drift Driven by Different Test Conditions
Temperature Dependency of the Threshold Voltage.Prior to the reliability tests, the temperature dependency of the threshold voltage has been recorded for both manufacturers.As shown in Fig. 2, not only the slopes of the Up and Down values are different, but they vary between both groups as well.Within the recorded temperature range V GS(T h) shows a linear dependency.Although the slope of V GS(T h)Down has a satisfying resolution for both groups, this parameter is not suitable for the junction temperature calculation due to the threshold voltage instability and hysteresis phenomena [2,7].1.In contrast to the PGM group, all trench SiC MOSFETs reached the end-of-life in the PCT.As expected, the EOLcondition remained the same and all specimens from the TGM group failed due to a V DS -increase.An opposing trend has been found for these two groups regarding the threshold voltage, as shown in Fig. 3 c) and d).The planar MOSFET showed a small V GS(T h) increase within the first 20, 000 cycles, partly resulting from the slight decline of the lower junction temperature (T vj(min) ), which was recorded shortly after the V GS(T h)Down measurement as shown in Fig. 1 b).After this peak the threshold voltage dropped for the specimen of the PGM group as depicted in Fig. 3 c).An interruption of the test occurred at approximately 267, 000 cycles, where the devices under test remained biased with a negative gate voltage (V GS = −10 V) for approximately 27.3 h, leading to an additional V GS(T h) drop due to the NBTI effect and finally reaching a saturation of the drift.The V GS(T h) -curve for the trench specimen was affected by a more pronounced decrease of T vj(min) , beginning from test start almost until test end.Therefore, the measured V GS(T h)Down values have been temperature corrected with the extracted slope (−4.8 mV K −1 ) from Fig. 2 b) and drawn together with the raw data in Fig. 3 d).A mean temperature of T vj(min) = 81.1 • C was calculated from roughly 425, 000 cycles until test end and was applied as targeted temperature for the data correction, because in this period T vj reached the static value.Especially within the first half of the test a significant deviation between measured and corrected V GS(T h) -values is clearly visible.The data correction was applied to the specimens from the PGM group as well, but the deviation remained negligible due to the minor decrease of T vj(min) (below 2 K) within the first 100, 000 cycles and the lower slope (−2.6 mV K −1 ).Therefore, both V GS(T h) curves are almost on top of each other in Fig. 3 c).

Solid-State Power Devices: Operational Reliability and Parameters' Stability
To identify a general V GS(T h) trend in the power cycling test, the V GS(T h)Down -drift was extracted and is shown in Fig. 4 for both groups.The measured threshold voltage has been temperature-corrected for all devices under test due to the non-stable T vj(min) during the PCT with the parameters shown in Fig. 2. Instead of the switching cycles, the V GS(T h)Down -drift was plotted vs. the test time in PCT, calculated according to the test period of T P CT = 6 s.The ratio between on-and off-state was 1 : 2. This condition led to a two times longer time, when negative gate voltage (V GS(of f ) = −10 V) was applied to the devices under test, then positive gate voltage (V GS(on) = 20 V).Occasional interruptions of the V GS(T h) read-out occurred during the test but this had no influence on the results.
Obviously, the specimens with planar gate structure had a non-uniform behavior during the test.Three out of fifteen specimens showed a significant drop between 2 h and 200 h, whereas V GS(T h) decreased with varying intensity beginning from 30 h until EOL for the remaining specimens after an initial growth.However, no correlation has been found between these devices, in terms of common test parameters such as temperature swing, virtual junction temperature or position in the setup (graphs not shown here).A contrary behavior has been observed for the TGM group where the threshold voltage increased for all fifteen devices under test in the same manner, as shown in Fig. 4 b).Therefore, it was possible to extrapolate the fit parameters for the MOSFETs with trench gate structure.For the extrapolation only values after 2 h have been considered.

Fig. 4: V GS(T h
) drift for a) planar and b) trench MOSFETs during the PCT in MOSFET-mode with a AC gate signal corresponding to the t on /t of f time; V GS(on) = 20 V and V GS(of f ) = −10 V with a ratio of 1 : 2; V GS(T h) read-out in situ at T vj(min) (approx.85 • C) with the hysteresis method; preconditioning for 100 ms at operating gate voltage; fit with power law as dashed line with factor A 0 and power law exponent b; temperature corrected data with slopes from Fig. 2 Threshold Voltage Drift in the HTGB.The results of DC HTGB tests are shown in Fig. 5 and Fig. 6 containing both groups, for positive and negative gate voltage respectively.Based on previously published results an increasing V GS(T h) was expected in the test with positive gate voltage (V GS = 20 V) [2,8,11].However, this behavior was observed for the TGM group only, whereas V GS(T h) dropped significantly for the specimens with planar gate structure.Increasing V GS(T h) is typically caused by charging effects of interface traps and/or oxide charges due to positive gate bias [1].Decreasing V GS(T h) is a typical indicator for mobile oxide charges, such as sodium or potassium ions, which is significantly enhanced by high temperature [2].
The drift in the NBTI test was less pronounced than in the PBTI test for both groups, potentially resulting from the lower absolute stress voltage level and opposite polarity.All specimens of the TGMgroup showed a slight V GS(T h) decrease in the NBTI test and the drift remained below 50 mV after 500 h.An opposing trend has been found for the MOSFETs with planar gate structure.Within the first 10 h the threshold voltage remained almost stable, below the initial value, but started to increase subsequently with test time.This behavior was probably caused by the same mobile charges, which Solid State Phenomena Vol.361 Fig. 5: V GS(T h) drift for a) planar MOSFETs and b) trench MOSFETs during the PBTI test at V GS = 20 V and T C = 150 • C for a test duration of t test = 500 h; in situ read-out of V GS(T h)Down at high case temperature with the gated-diode configuration at I D = 1 mA and an acquisition delay time of t aq(del) = 1 µs; fit with power law as dashed line with factor A 0 and power law exponent b led to a V GS(T h) decrease in the PBTI test.Negative gate bias attracted mobile ions, such as Na + and K + , in the oxide close to the gate metallization.Consequently, a higher gate voltage was necessary to create an inversion channel at the SiC/SiO 2 -interface.To the bipolar gate switching of the PCT, SiC MOSFETs have been to a periodically alternated stress test.The impact of and negative gate bias clearly visible in Fig. 7, with circles and asterisks representing the V GS(T h) after stress with positive and gate bias, respectively.Resulting from the stress period of 0.1 h positive gate voltage, V GS(T h)Down decreased for the PGM group, shown Fig. 7 a).After the subsequent stress neggate bias for 0.1 h V GS(T h)Down decreased further.With logarithmically time in every stress period for the PBTI part the gap between the GS(T h) drift became more significant.Comparing these results with Fig. 5  Due to different behavior in the DC gate stress tests of the SiC MOEFETs with trench gate structure, the results from the Alt-BTI test deviated significantly from the test of the PGM group.However, the V GS(T h) drift correlates to the results shown in Fig. 5 b) and Fig. 6 b).Positive gate bias led to a V GS(T h) increase, whereas the negative gate bias counteracts the drift.This behavior became more pronounced with increasing test time.Like the results from the PGM group, the final threshold voltage after 1000 h was between 50 mV and 100 mV higher than the initial value.To ensure a justified comparison between the V GS(T h) -drift in the PCT and the Alt-BTI test, only the values recorded after the NBTI part have been considered for the fit parameters extraction.

Discussion and Conclusion
Returning to the motivation of this paper, the experimental attempt to model the PCT-driven V GS(T h) drift with different gate stress tests, it becomes evident that no general approach has been found.Especially, due to the complicated and non-uniform drift behavior of the PGM group in the PCT, it was hardly possible to extract reliable fit parameters.Taking the gate stress tests into account, the SiC MOSFETs with planar gate structure indicate the presence and interaction of different mechanisms, affecting the V GS(T h) drift, including interface states and oxide charges.In contrast to the PGM group, the SiC MOSFETs with trench gate structure showed a homogeneous and predictable V GS(T h) drift in the PCT, remaining below 100 mV.In this case, the fit results from PBTI and Alt-BTI test came close to the parameters extracted from the PCT.Especially, the power law exponent b is in the same range for all three tests, whereas the lowest factor A 0 has been extracted from the PCT.This behavior results most likely from the typical temperature swing in the PCT, leading to a slightly lower V GS(T h) drift.

Summary
Threshold voltage instability remains a challenging aspect of SiC MOSFETs.Beside the standard approaches to analyze the V GS(T h) drift in gate stress tests, the impact on power cycling tests became evident as well.Depending on manufacturer or rather manufacturing process and/or MOS structure, the drift intensity and polarity might vary significantly.Only for one out of two test groups, the extracted power law fit parameters were in a comparable range between power cycling and gate stress Solid State Phenomena Vol.361 tests.Therefore, it is highly recommended to implement the V GS(T h) read-out procedure in power cycling tests of SiC MOSFETs.

Fig. 1 :
Fig.1: a) Simplified circuit diagram for the determination of V GS(T h) and T vj in the PCT; b) pulse pattern of gate voltage and measurement timings of T vj and V GS(T h) ; V GS(T h) read-out in alignment to the hysteresis method from the JEDEC standard JEP 184 and[2] shortly before T vj(min) measurement; c) sample measurement on a SiC MOSFET during the PCT; delay between load-current turn-off event and T vj(max) measurement was 200 µs; detailed description of the test setup in[5].

Fig. 2 :
Fig.2:V GS(T h) vs. T vj for a) planar and b) trench MOSFET; V GS(T h) measured with the triple sense method according to the JEP 184 standard, including records of the V GS(T h)U p and V GS(T h)Down in the gated-diode configuration (V GS = V DS , I D = 1 mA); the acquisition delay time set to t aq(del) = 1s; a preconditioning prior to every V GS(T h) measurement has been applied to specimens with a gate voltage of V GS = ±20 V for a fixed pulse time of t precon = 100 ms Threshold Voltage Drift in the PCT.Representative PCT results from each group are shown in Fig.3, including trends of forward voltage drop (V DS ), thermal resistance (R th(jhs) ) and junction temperature swing (∆T vj ) in a) and b).For the PGM group only 6 out of 15 specimens reached the EOL condition due to a V DS -increase by more than 5 % from the steady state value and 9 devices did not fail until the test end after 450, 000 cycles.V DS -increase is a typical EOL-criterion for semiconductor power devices in TO-packages in power cycling tests and indicates either bond-wire lift-off or heel crack as failure

Fig. 3 :
Fig. 3: R th(jhs) , V DS and ∆T vj in a) planar and b) trench MOSFET together with V GS(T h)Down and T vj(min) in c) and d); planar MOSFET reached EOL after approx.000 cycles as shown in a); trench MOSFET reached EOL after 487, 000 cycles as shown in b); slight decrease of T vj(min) for the trench device in d) affecting V GS(T h)Down read-out; measured and temperature-corrected V GS(T h)Down value shown in c) and d); test of planar device restarted around 267, 000 cycles in c)

Fig. 6 :
Fig. 6: V h) drift for a) planar and b) trench MOSFETs during the NBTI test at V GS = −10 V and T C = 150 • C for a test duration of t test = 500 h; in situ read-out of GS(T h)Down at case temperature with the gated-diode configuration at D = 1 mA and an acquisition time of t aq(del) = µs; fit power law as dashed line with A 0 and power law exponent

Fig. 7 :
Fig. 7: V GS(T h) drift for a) planar and b) trench MOSFETs during the Alt-BTI test at V GS(on) = 20 V, V GS(of f ) = −10 V and T C = 150 • C for a total test duration of t test = 1000 h, including 500 h PBTI and NBTI stress with equal share; in situ read-out of V GS(T h)Down at high case temperature with the gated-diode configuration at I D = 1 mA and an acquisition delay time of t aq(del) = 1 µs; fit with power law basing on the drift after the NBTI part

Table 1 :
[9]t conditions of the PCT in MOSFET-mode[9]for 1.2 kV SiC MOSFETs . The shown planar SiC MOSFET reached end-of-life after more than 367, 000 cycles, whereas the first failure occurred after approximately 240, 000 cycles (not shown).This deviation results from different individual temperature swing in the test, as shown in Table ).For the PGM group only 6 out of 15 specimens reached the EOL condition due to a V DS -increase by more than 5 % from the steady state value and 9 devices did not fail until the test end after 450, 000 cycles.V DS -increase is a typical EOL-criterion for semiconductor power devices in TO-packages in power cycling tests and indicates either bond-wire lift-off or heel crack as failure Solid State Phenomena Vol.361 mechanism