Demonstration of SiC Trench Gate MOSFETs with Narrow Cell Pitch Using Source Self-Aligned Process

The SiC trench gate MOSFET with narrow cell pitch is demonstrated using a process in which the n+ source is self-aligned to the trench gate. A minimum cell pitch of 1.6 μm, which is difficult to achieve using the conventional device structure, is easily fabricated by applying a deep n+ source and a buried interlayer dielectric structure. The cell pitch reduction indicates a beneficial trend that contributes to a decrease in the specific on-resistance and an increase in the breakdown voltage. The process and structure are promising for further improving SiC power device characteristics.


Introduction
SiC trench gate MOSFETs are generally more suitable than planar gate MOSFETs for cell pitch (Wcell) reduction. A narrow Wcell is desirable to reduce the specific on-resistance (RonA), especially below the 1200 V-class, where the ratio of the channel resistance is high. However, a Wcell reduction causes difficulties in the alignment and patterning processes. The self-aligned process is utilized to overcome these issues. Recent studies have reported the conventional type of single-trench gate MOSFETs (ST-MOSFETs) using the self-aligned process, such as the p + shielding region under the gate trench and the segmented contact regions [1][2][3][4]. With further reduction in Wcell in the ST-MOSFETs, difficulties in establishing ohmic contact appears due to the contact aperture limit are observed next. In this study, we developed an n + source self-aligned process adjacent to the gate trench, which realizes the stable fabrication with narrow Wcell = 2.0 μm or less, and demonstrated deep-channel MOSFETs (DC-MOSFETs) fabricated using this self-aligned process. This device has a deep n + region and a buried interlayer dielectric (ILD), which allow for a significantly narrow Wcell.

Design Concept and Fabrication
where Wt is the trench width; Wn is the n + width; Wp is the p + width; WGS is the gate-source (GS) distance; and Wnf = Wn -WGS is the n + footprint width. WGS requires a certain thickness to obtain a low GS failure rate and low GS capacitance. Additionally, if the ILD width and its aperture width are defined as Wline and Wspace, respectively, Wcell reduction sacrifices Wspace owing to the constraint Wline = Wt + 2WGS. Consequently, the ILD aperture and metal coverage failure associated with Wspace reduction, and ohmic contact failure where Wnf < 0, are likely to occur because of Wspace = 2Wnf + Wp.
On the other hand, Wcell in the DC-MOSFET is given by W cell = W t + 2W n + W p = W t + 2W nf + W p .
It follows that Wnf = Wn. Because the n + source is formed deeper than that in the ST-MOSFET, the gate electrode is formed deeper, and the ILD is buried in the trench. Thus, a certain thickness of WGS is retained in the vertical direction, and WGS is excluded from the cell parameters, which allow the DC-MOSFET to reduce the Wcell significantly. Furthermore, the strict alignment control at the ILD aperture is unnecessary because Wline only needs to satisfy 0 ≤ Wline < Wt. The ILD aperture, metal coverage, and ohmic contact failure do not occur easily because Wspace is maintained wider than that in ST-MOSFET. As stated above, the DC-MOSFET is advantageous in reducing the Wcell with stable processes.  Figure 2 illustrates the main fabrication procedure for the DC-MOSFETs. A drift layer, which concentration and thickness were 1.5×10 16 cm -3 and 4.7 μm, was prepared on a substrate for the 650 V-class, and a current spreading layer (CSL) was then stacked on the drift layer. The bottom half of the n + and p-base regions were formed via ion implantation in the first in-process epitaxial growth layer, whereas the upper half of the n + source region was formed via ion implantation in the second in-process epitaxial growth layer. Subsequently, without removing the SiO2 hard mask, the first SiO2 sidewall was formed, and a SiC trench narrower than the width of the P implantation was formed by dry etching. A p + shielding region was then formed by Al implantation with the second SiO2 sidewall. Therefore, both the p + shielding region and n + source region were formed using the self-aligned process to the trench gate.

64
Engineering Materials: Research and Application Optimization

Experimental Results
Demonstration. Figure 3 shows the cross-sectional SEM image of (a) ST-MOSFET with Wcell = 2.0 μm and (b) DC-MOSFET with Wcell = 1.6 μm. The DC-MOSFET was fabricated using the n + source self-aligned process, whereas the ST-MOSFET did not use the process. For the ST-MOSFET, an Al void and a short Wnf due to the narrow Wspace were observed. Moreover, because Wnf is slightly different on the left and right sides of the trench gate owing to the misalignment of both the upper half of the n + source region and the ILD aperture to the trench gate, there is a concern that Wnf < 0 μm on at least one side when Wcell < 2.0 μm. However, for the DC-MOSFET, the Al coverage is satisfactory because of the relatively wide Wspace, and Wnf is also wide enough. Wnf is formed equally on both sides of the trench gate because it is not affected by the misalignment of the ILD aperture when Wline < Wt. Thus, owing to the ability to form the WGS in the vertical direction, trench gate MOSFETs with Wcell < 2.0 μm are easily realized.   . The reduced cell pitch shows a trend toward reduced RonA, especially for the DC-MOSFETs, where the smallest RonA was obtained. This suggests that the effect of the decrease in Rch owing to the increased channel density is larger than that of the increase in the JFET resistance (RJFET) owing to the wide JFET width, even at Wcell = 1.6 μm. The solid lines representing the measurement results include the substrate resistance (Rsub) with thickness of 360 μm and 333 μm for ST-MOSFETs and DC-MOSFETs, respectively. The dotted lines represent the case where the substrate thickness is reduced to 100 μm (Rsub = 0.20 mΩcm 2 ). Particularly, for the DC-MOSFETs with Wcell = 1.6 μm, the RonA is reduced to 0.75 mΩcm 2 . Figure  5 (b) presents the simulated results of the RonA components for the DC-MOSFET with Wcell = 1.6 μm. Excluding the removable substrate resistance of 0.47 mΩcm 2 , Rch is regarded as the largest component despite the high channel density. It suggests that further RonA reduction is possible by reducing Wcell less than 1.6 μm, shortening the channel length (Lch) and improving the mobility (μFE). For example, in DC-MOSFETs with Wcell = 1.4 μm, if Lch is halved and μFE is doubled, RonA is expected to be 0.55 mΩcm 2 . In this study, Lch and μFE are about 0.46 μm and 23 cm 2 /Vs, respectively.   Figure 6 (b) shows the simulated results of the electric field at VDS = 650 V for the DC-MOSFETs with each Wcell. The cell pitch reduction suppresses the electric field for the shielding structure at the bottom of the trench gate. This is attributed to the suppression of the potential drop near the channel. Additionally, a reduction in the Wcell also contributed to the relaxation of the electric field for the gate oxide at the bottom corner of the trench gate, which is advantageous for improving the reliability of the trench gate structure. Figure 7 exhibits the RonA and VB trends for the Wcell reduction. The results up to Wcell = 1.6 μm demonstrated in this study indicate that both the RonA and VB characteristics improve simultaneously with the Wcell reduction. The RJFET does not increase under this CSL concentration of 6.0×10 16 cm -3 because the JFET width of 0.9 μm is wide even with Wcell = 1.6 μm. The novel structure and process for DC-MOSFETs which enable easy fabrication of the device with Wcell < 2.0 μm reveal that further Wcell reduction and characteristics improvement are possible in the future.

66
Engineering Materials: Research and Application Optimization

Summary
The first prototype DC-MOSFET applying the n + source self-aligned process was demonstrated. DC-MOSFETs with a deep n + source and buried ILD can reduce the Wcell efficiently than conventional ST-MOSFETs, and are less prone to process failures. The DC-MOSFET with a minimum Wcell of 1.6 μm was demonstrated, and it exhibited RonA = 0.75 mΩcm 2 (in the case of a substrate thickness of 100 μm) and VB = 750 V. Because the reduced Wcell can simultaneously improve the RonA and VB characteristics, the DC-MOSFET using the n + source self-aligned process is one of the promising structures for further development in SiC power MOSFETs.