UIS Ruggedness of Parallel 4H-SiC MOSFETs

. We have studied the UIS (Unclamped Inductive Switching) ruggedness of SiC MOSFETs in parallel. We show that UIS ruggedness of parallel MOSFETs is a function of the difference in their breakdown voltage (Δ - BVDSS). As expected, for large Δ -BVDSS UIS, ruggedness is dominated by the lower BVDSS transistor. Somewhat unexpectedly, for small enough Δ -BVDSS, UIS ruggedness is better than the sum of its two transistors. Specifically, the energy that parallel transistors of low Δ - BVDSS can sustain depends on the peak current and is 10%-20% higher than the sum of the energies of the individual transistors. We explain the physical mechanism of this effect and extend the concept to the case of more than 2 parallel transistors. These findings are important for the efficient design of power circuits with multiple die in parallel.

We observe, that: 1.) The breakdown energy E depends on the peak current Ip and the difference between Δ  of the individual FETs:   decreases with Ip -0.6 and decreases with Δ  with a rate of approx.10 mJ/V 2.) For small Δ-BVDSS the solid lines exceed the dotted lines, i.e. the pair of parallel FETs can withstand an energy larger than the sum of two individual FETs.3.) As Δ  ≫ 0 and   of the pair tapers off, the theoretical minimum is not reached by Δ  =60V Before discussing these results of UIS ruggedness of a pair of parallel MOSFETs it is helpful to recapitulate the theory of UIS ruggedness of a single MOSFET as presented in [2].The main failure mechanism is due to the thermal runaway and melting in the metallization (Aluminum) caused itself by the self-heating from the power dissipation in the MOSFET in avalanche.In [2] it was shown that this, together with a power law of zth(t)=t q /ĉ for the transient thermal impedance zth, leads to a relationship whereby ΔTcrit is a critical junction temperature [3]. Figure 2 plots the relationship E~Ip  , whereby =1-1/q for single FETs from C3M0075120.This plot explains the E↔Ip observation listed above.In order to explain the observed E↔ ΔVav relationship it is helpful to compare the waveforms of the individual FETs with waveforms of the pair for two cases: large and small ΔVav.Unexpectedly, the UIS ruggedness of a pair exceeds the sum of the two individual FETs.We refer again to the waveforms presented in figure 3. On close observation, it can be seen, that the waveform of the pair rises slightly slower and has a slightly lower peak voltage and earlier finish.The root cause lies in the positive avalanche temperature coefficient [4], which leads to a thermal balancing: As one FET heats up, its ΔVav increases and it thus offloads current to the other FET.
This result can also be discussed in the framework of the above-mentioned model for UIS ruggedness [2].According to the link established between the transient thermal impedance zth(t)=t q /ĉ and the energy versus peak current relationship E~Ip  with =1-1/q, a smaller q comes along with a steeper slope in the E↔Ip relationship.Figure 4 illustrates this.The data from figure 1 is replotted as a function of Ip, parameterized by ΔVav with different colors It can be seen, that the slope of the pairs is steeper than the slope of the single FET (black curve as in figure 2).This result can be illustrated in yet a different manner.As shown in [2], it is possible to extract zth and subsequently q directly from the waveform V(t): where TCBV is the temperature coefficient of the avalanche voltage, Rs is the series resistance of the current path (extracted alongside with q) and τav is the time in avalanche.Figure 5 plots on the left the relationship =1-1/q and illustrates that a smaller q leads to a more negative  and thus a steeper E~Ip  relationship.On the right the q-exponents of the individual FETs vs. the q-exponents of the pairs extracted according to the formula above (Green: 10A on the pair, Blue: 20A; Pluses and Dots refer to the 1st and 2nd FET).For most devices the individual q-s are larger than the q-s of the pair.According to (1) E scales inversely with q-s.

UIS Ruggedness of Four Parallel MOSFETs
Finally, we present data for four FETs in parallel.Figure 6 shows the data arranged in a similar fashion as in figure 1.The conclusions for the 4 FETs case are the same as for the 2 FETs case.

Conclusions
In conclusion, we present data for UIS ruggedness of 4H-SiC MOSFETs in parallel.We show its dependency on peak current and the difference in breakdown voltage of the single FETs.We show and explain that for sufficiently small Δ-BVDSS the UIS ruggedness of a pair of parallel pairs of FETs surpasses the sum of the ruggedness of the individual transistors.Effective binning of FETs by BVDSS can be chosen very generously or is unnecessary when designing for UIS robustness.Fig. 5. Relationship between the exponent  from E(Ip) and the exponent q of zth(t)=t q/ĉ as described in [2] Right: q of the individual FETs vs. q of the pair.Green: 10A on the pair, Blue: 20A; Pluses, Dots refer to the 1 st and 2 nd FET.

Fig. 1 .
Fig.1.Failure energy per FET of pairs of FETs as a function of Δ-BVDSS for 5 peak (pair-) currents (magenta =40A, blue=20A, green=10A, orange=8A, red=7A).Dotted lines left show failure energies for single FET at half currents, dotted lines right show failure energies for single FET at full current (divided by 2).

Fig. 2 .
Fig. 2. Failure energies as a function of peak current Ip for C3M0075120.

Fig. 6 .
Fig. 6.Failure energy per FET of quads of FETs as a function of Δ-BVDSS for 4 peak (pair-) currents (magenta=80A, blue=40A, green=20A, red=14A).Dotted lines left show failure energies for single FET at half currents, dotted lines right show failure energies for single FET at full current (divided by 4).