Frequency Investigation of SiC MOSFETs C-V Curves with Biased Drain

. SiC MOSFETs still suffers from some open issues, such as the high density of defects existing at the SiC/ SiO 2 interface. In order to characterize such interface, a non-destructive investigation technique should be employed. In this work, we investigate the measurement of Gate capacitance with biased Drain. More in detail, the effect of frequency on such curves is considered. The analysis is performed using both in experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region which reduces its height as frequency increases.


Introduction
Silicon Carbide (SiC) MOSFETs are playing an increasingly significant role in today's power industry.They are gradually replacing Silicon (Si) MOSFETs, because of the excellent properties of SiC, such as high thermal conductivity and high bandgap [1].Despite the wide technology development of last years, there are still some issues to be fixed.For example, the high density of defects at the SiC/SiO2 interface is a relevant problem.Defects at such interface can influence the overall performance of the device [2], causing detrimental impacts on threshold voltage stability [3], channel mobility [4] and leakage current amplitude.Due to the fundamental importance of the SiC/SiO2 interface characterization, several techniques have been employed in literature to investigate defects properties related to this region.However, the chosen technique should be nondestructive and low time consuming to ensure a fast and repeatable characterization.The most exploited methods in literature rely on the measurement of the capacitance [5]- [9] arising at low and high frequency.Such technique is indeed useful in the MOS structure where the capacitance behavior varies substantially with frequency [10].This occurs since the inversion charge can follow the AC stimulus only for low frequency because of the low thermal carrier generation rate in the depletion region.Thus, the capacitance behavior in the inversion region, mainly due to the inversion charge, cannot follow the AC stimulus with high frequency either.This circumstance standing for a MOS structure is not valid for a MOSFET structure, where the channel in the inversion region is replenished of carriers coming from the Source and Drain regions.This means that the capacitance trend in the inversion region does not vary at low and high frequency.Hence, such method cannot be applied to MOSFET structures [11].This outcome suggests that the capacitance measured from a MOSFET should be analyzed and studied using numerical frameworks if the SiC/SiO2 interface needs to be characterized [12]- [16].The measured capacitance is usually the Gate capacitance, and the experiments are done by applying the stimulus on the Gate and connecting Drain and Source terminals [17]- [19].
In our previous work [15], [20], [21], we carried out a non-classical C-V measurements on commercially available planar SiC MOSFETs.The stimulus is applied on the Gate, while a fix DC bias is applied on the Drain and the Source terminal is grounded.The resulting capacitance exhibits a sharp peak in the inversion region, which is not expected.This peak is related to the interface properties and the channel region.In this work, a frequency analysis is performed both in experimental and numerical framework.Given that traps dynamics influence the arising capacitance, frequency is a crucial parameter while characterizing SiC MOSFETs.The variation of the obtained Gate capacitance with frequency is in fact due to the different behavior of existing traps/impurity with frequency.Traps can follow slow frequency signals while it is not the case for high frequency.The experimental results are supported by numerical analysis performed in Sentaurus TCAD.Both analyses show that the capacitance peak arising in the inversion region reduces its height as the frequency increases.

Experimental Results
Experiments are obtained using the setup of Fig. 1, the capacitance is measured between Gate and Source terminals, while a DC bias is applied to Drain terminal, VDS.The capacitance measured in this configuration shows a non-negligible peak centered at a voltage close to the threshold voltage, Fig. 2. The mentioned peak is higher as the applied Drain voltage increases.In previous works, we related the peak shape to traps in the channel region [15] and a complex electric field/free charges dynamics is assumed to be responsible for this phenomenon.The effect of frequency on the so measured capacitance has been considered in this work.The experimental results are obtained from an experimental 1200 V SiC MOSFET commercially available and the measured curves are presented in Fig. 3. Frequency has been swept from 10 kHz to 400 kHz, while the imposed VDS has been set to 0.2 V.The obtained curves show that the capacitance peak reduces with increasing frequency.

Numerical Setup
The numerical analysis has been performed in Sentaurus TCAD.The structure considered in this work is presented in Fig. 4.An AC small signal analysis is performed in order to obtain the capacitance behavior [12].Numerical curves are presented in Fig. 5.It can be seen that the numerical capacitance curves obtained exhibit a sharp peak, in the inversion region, which reduces its height as the frequency increases.Numerical curves show the same behavior of experimental results: the capacitance peak becomes less prominent at higher frequency.

Fig. 1 .
Fig. 1. a) Experimental setup used; b) Gate Voltage and c) Drain voltage applied during measurements.

Fig. 3
Fig. 3 Experimental C-V curves obtained at increasing frequency values, with a VDS =0.2 V.

Fig. 4 .
Fig. 4. Structure built in Sentaurus TCAD.The structure is not to scale.

Fig. 5 .
Fig. 5. Numerical C-V curves obtained at different frequency values, from structure of Fig.4.