Demonstration of 800 °C SiC MOSFETs for Extreme Temperature Applications

. Silicon Carbide (SiC) enhancement mode MOS electronics offer several benefits for realizing analog, digital and mixed signal electronics, but limitations on gate dielectric reliability has limited the adoption of MOS in high temperature application. In this work, we report GE’s lateral SiC MOSFETs exceeding previously reported temperature capabilities for SiC MOSFETs with experimental results that have shown that >500°C operation of SiC MOSFETS is possible with >400 hours demonstrated at 620°C, and short-term functionality demonstrated to 800°C. The result shows that MOS-based SiC electronics can continue to be a viable choice for circuit implementations at extreme temperatures >600°C.


Introduction
Silicon carbide (SiC), as a wide band gap semiconductor, can replace Si and silicon-on-insulator (SOI) for extreme temperature (>500°C) applications such as space exploration, oil and gas downhole control and instrumentation, and geothermal.Currently, junction field-effect transistors (JFETs) and bipolar junction transistors (BJTs) are being considered as potential SiC device technologies for operating at temperatures beyond 500°C [1][2][3].Compared to JFETs and BJTs, MOSFETs offer several advantages to the circuit designer.The high input impedance of MOSFETs is advantageous for sensor signal conditioning where low input current is needed.Enhancement mode MOSFETs do not require negative gate voltages to turn device off and eliminate the need for inclusion of level-shifters between stages, thereby simplifying the circuit design.Extension to complementary MOSFET (CMOS) provides low static power dissipation [4] which enables scalability towards more complex digital implementations.SiC MOSFET-based circuits have been historically limited in their maximum temperature due to gate oxide interface leakage [5].However, recent advancements in gate oxide fabrication [6] have enabled MOSFETbased integrated circuits to hold promise for high-temperature electronic applications that were previously only achievable with JFET or BJT devices.

Prior Testing
GE has previously reported on SiC MOSFET based electronics testing over an extended temperature range from -193°C to +500°C [7].The testing has demonstrated operation over 100 hours at 500°C, and functionality over the entire temperature range.This testing was conducted on circuits built with NMOS SiC lateral devices.Testing was then extended to include both NMOS and PMOS devices, where a CMOS inverter was tested for 60 at 500°C [4].This work expands on the previous testing by extending the temperature range to 800°C. it further reports on >400 hours of testing at 620°C and extends the gate reliability modeling by conducting time dependent dielectric breakdown (TDDB) testing at 620°C.

MOSFET Testing at 800°C
The 800°C data was conducted in an oven.The samples were packaged by attaching the SiC chip to an Alumina ceramic substrate with Au thick film interconnect printed onto the substrate.Au wirebonds were utilized to interconnect the SiC die to the ceramic substrate and to interconnect the device carrier and the wiring substrates.Pt wire was used to wire the assembly to the instrumentation outside the oven.Multibore ceramic tubes were used to separate the wires and prevent shorting during testing.The Pt wires were routed through holes drilled through the wiring substrate, which acted as a strain relief for the wires.A Zircar cement was used to adhere the multibore ceramic tubes to the wiring substrate assembly.
The test assembly is shown in Fig. 1.The assembly was placed in an oven equipped with a nitrogen purge gas.The nitrogen purge was used in order to isolate semiconductor failures from back end of line (passivation and metallization) failures.The sample wires were routed to a semiconductor parameter analyzer (Fig. 2).The temperature was stepped from room temperature.Drain current (Id) versus gate voltage (Vgs) data was collected.The device functioned up to 800°C, but a failure occurred when the temperature was stepped to 825°C (Fig. 3).Temperature dependent device threshold voltage and transconductance were extracted and shown in Fig. 4. A constant-current threshold voltage was calculated as the current at which the drain current reaches 5µA.The transconductance was extracted at one volt higher than the calculated threshold voltage.Form the above results, the threshold voltage drops as a function of temperature, but remains positive up to 800°C, indicating that the enhancement-mode operation of the MOSFET is preserved.The transconductance continues to increase up to 700°C, remains relatively flat until 750C then starts decreasing.At 800°C, the transconductance approximately half that of the room temperature value, and approximately 6.75x lower than the peak transconductance which occurred at 700°C.

Extended duration Testing at 620°C.
Testing at temperatures up to 620°C was conducted utilizing diced bare die.The test die contains a number of individual lateral 4-terminal MOSFETs.The test setup utilizes a Signatone manual probe station with a heated chuck.A thermocouple was placed on a test sample and utilized to characterize the device under test (DUT) temperature against the probe station's chuck set point (Fig. 5).
Fig. 5 DUT temperature as a function of chuck temperature setpoint.Drain Current (Amperes) Gate voltage (volts) The 620°C measurements were obtained on our high temperature probe station in air.The gate voltage was held at 20 V for the entire test duration.IV sweeps were conducted periodically to confirm device operation.The SiC MOSFETs have shown continuous operation for 400 hours at 620 °C (Fig. 6).An increase in off state leakage was observed between and 96 hours of testing.The test probes were repositioned on the device which alleviated the leakage and testing continued for >300 hours of additional test time.The leakage may be due to surface leakage between two adjacent probes, but the root cause for the leakage is unconfirmed at this point.

Drain Current versus Gate Voltage
It was observed that the gate leakage current started increasing after 410 hours, and the device was deemed to have failed at 412 hours of testing when the leakage reached 100µA as shown in Fig. 7.
The gate leakage data was recorded on a 1-minute interval for the duration of the test.At the conclusion of the testing, the DUT was removed for optical inspection.The DUT showed significant passivation and metallization deterioration after testing (Fig. 8).GE has previously tested several chip metallization and passivation options for operation at >500°C [7].Subsequent device fabrication will utilize the improved high-temperature, high-reliability metallization and passivation identified.

Gate oxide reliability
We conducted high-temperature time dependent dielectric breakdown (TDDB) testing by applying a voltage over-stress to the gate and recording time to failure at 350°C and 400°C [8].The measurements were extended to 620°C.An Arrhenius model was fit.The lines on Fig. 9 show the mean lifetime with 95% confidence interval of the failure distribution.An extrapolation to 800°C based on the extracted model parameters shown in Fig. 10.

Fig. 2 Fig. 3
Fig. 2 Oven test setup a) test board in oven with wiring leading to outside instrumentation.b) Test instrumentation showing test PC with semiconductor parameter analyzer

Fig. 4
Fig.4MOSFET threshold voltage and transconductance dependence on temperature.

Fig. 6
Fig. 6 Drain current versus gate voltage at 620°C over time.

Fig. 8
Fig. 8 Optical image of SiC MOSFET test die a) at beginning of high temperature testing b) after 412 hours at 600°C.

Fig. 9
Fig. 9 TDDB testing shows lifetime versus gate voltage for SiC MOSFET