Impact of Turn-Off Gate Voltage and Temperature on Threshold Voltage Instability in Pulsed Gate Voltage Stresses of SiC MOSFETs

Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.


Introduction
Power semiconductor devices are required to pass high temperature gate bias (HTGB) stress tests which comprise of 1000 hours of gate voltage bias at a high temperature. The Threshold voltage (V TH ) is required to remain strictly within defined limits specified by the datasheet [1]. For silicon MOSFETs and IGBTs, this is routine. Although the latest generation of SiC MOSFETs have passed this reliability tests, measurements still show considerable V TH shift compared to silicon devices. Gate oxides in SiC MOSFETs are reported to have lower breakdown voltages and are less robust under short circuit conditions [2,3]. This is due to higher fixed oxide and interface trap density resulting from the oxidation of SiC to form the gate oxide [4]. The presence of carbon atoms during thermal oxidation of SiC means dangling bonds at the oxide interface which become interface traps that can hold both positive and negative charges thereby shifting the flat-band (and threshold) voltage [4,5]. In high frequency applications where the SiC MOSFET experiences large dI DS /dt and dV DS /dt, to prevent short circuits resulting from Miller capacitance coupling, SiC MOSFETs are usually turned-OFF with a negative gate voltage. This means that the gate oxide traps holes and electrons in rapid succession as the device is switched at high frequencies.
Previous studies have shown that threshold voltage shifting due to positive and negative bias temperature instability is a significant challenge in SiC MOSFETs [6,7]. Another important consideration regarding gate reliability measurements in SiC MOSFETs is the recovery time, which is the time duration between the removal of the V GS stress pulse and the measurement of V TH . The MOSFET V TH recovers towards its pretest value as the stress pulse is removed since trapped charges are released. In positive HTGB where the V TH shift is positive due to electron trapping, the trapped electrons are released after the V GS is set to zero. Furthermore, the recovery of the V TH can be accelerated by applying a negative V GS . Hence, the measurement of V TH during HTGB tests in SiC MOSFET must follow a defined procedure with a predefined recovery time and preconditioning.
Until recently, mainly unipolar constant gate stresses were investigated as has historically been the case when testing silicon devices on high temperature gate bias. Some studies have shown the impact of pulsed gate voltage stresses on threshold voltage shift in SiC MOSFETs [8]. It has previously been demonstrated that using a turn-off gate voltage of -5V is capable of mitigating positive V TH shift from PBTI during pulsed stresses of SiC MOSFETs at 100 kHz switching frequency [9]. This paper investigates the comparative effectiveness between turn-off gate voltages of -3 V and -5 V in suppressing PBTI. Pulsed PBTI experiments are performed over a frequency range from 1 Hz to 100 kHz on two commercially available SiC MOSFETs at 25°C and 150°C. Preconditioning is performed prior to the classic measure-stress-measure sequence to ensure a known state of charge prior to measurement [10]. A recovery time of 20 milliseconds is used in the measurements and the duty cycle of the pulses is set at 50%.

Experimental Measurements
The experimental set-up shown in Figure. 1 comprises of Source Measuring unit (SMU) 2602B from Keithley for measuring threshold voltage, a gate driver with adjustable turn-off voltages, a small electric heater for setting the junction temperature and relays for controlling the circuit and switching from stress-mode to measurement mode. The devices under test (DUT) are commercially available 1200V SiC power MOSFETs. A Planar MOSFET and a Trench MOSFET from well-known device manufacturers have been selected.

b). Custom designed PCB for pulsed gate stresses application and VTH measurements
During stress mode, the MOSFET drain-source is shorted, and the gate-source is connected to the gate driver as shown in Figure. 2 (a). TTL pulses are generated using a National Instruments board model NI-USB-6210 and are connected to the gate driver board input. The duty ratio of the pulses is 50% and the on-state gate voltage (V GS-ON ) is set as the recommended gate voltage for the DUT. The off-state gate voltage (V GS-OFF ) is varied (0V, -3V, -5V). In Figure. 2 (b), the measurement mode is shown. Here, the gate and drain terminals are shorted and 1 mA is sourced through the DUT from the SMU which measures the V TH as the V DS . The test sequence is shown in Fig. 2(c). The switching frequency of the gate pulse is varied from 1 Hz to 100 kHz logarithmically.
A preconditioning pulse is recommended, [10] to define a state of charge in the gate oxide before   Figure 3 shows the results of 1000 seconds of positive HTGB measurements with a V GS pulse frequency of 60 kHz, a duty cycle of 50% and using the pulse sequence defined in Figure 2(c). Figure 3(a) shows the results for the unipolar test (V GS-OFF = 0V) while Figure 3(b) shows that for the bipolar test (V GS-OFF = -3 V). Both tests in Figure 3 have been performed with a silicon MOSFET from IXYS with datasheet reference IXFK20N120 for comparison. The results in Figure 3 shows that the V TH shift from the bipolar V GS pulse is smaller compared to that of the unipolar V GS pulse. The difference in V TH shift between the unipolar and bipolar stress pulses is more apparent in the Planar MOSFET (device A) than in the Trench MOSFET (device B). It is clear that the V TH shift in the silicon MOSFET is negligible compared to those in the SiC MOSFET. Figure 4 shows the impact of the switching frequency on the V TH shift with the unipolar V GS pulse and two bipolar V GS pulses (V GS-OFF = -5 V and -3 V). The V TH shift is calculated for each frequency step. The result show that the overall V TH shift increases with frequency between 1 Hz and 1 kHz for

DUT D G SMU R G S
all V GS stresses. Beyond 1 kHz, the V GS shift is constant and independent of frequency. When V GS-OFF = -5 V, the overall V TH shift becomes negative. When V GS-OFF = -3 V, the V TH shift is close to zero for most of the switching frequencies. This indicates that -3 V is an optimal turn-OFF voltage as far as minimizing V TH shift is concerned. Figure 5 shows the impact of temperature on the V TH vs Frequency characteristics of the SiC Planar MOSFET (device A) and the SiC Trench MOSFET (device B). The overall negative shift in V TH is increased at 150°C indicating either faster electron release with increasing temperature, more hole trapping with increasing temperature or a combination of both.

Accelerated Stress Tests
By applying a constant gate voltage of 30V (significantly more than the rated gate voltages) to the gate of the power MOSFETs, the ΔV TH has been accelerated. 30V was applied to the gate of the SiC MOSFETs for 1000 seconds and the ΔV TH has been measured at different points after the stress removal. The objective here was to understand the V TH recovery of the devices. The initial shift of the V TH is higher compared to the V GS stress at the rated voltage due to the higher electric fields imposed on the gate oxide. These tests have been performed at 25°C and 150°C junction temperatures. Figure 6(a) shows the results of the recovery measurements at 25°C while Figure 6(b) shows the similar plot for measurements done at 150°C. Measurements were also performed on a silicon MOSFET for benchmarking. The shifts reported in the SiC Trench MOSFET (device B) are higher than those in SiC Planar MOSFET (device A). It is also clear that the time constant of the trapped charge in device B are larger since it takes a longer time to recover. It should be noted that these measurements were performed without preconditioning, hence, what is under observation is V TH shift due to charges with short time constants. Figure 7(a) shows the results of an oxide breakdown test. Here, the V GS is swept upwards until the leakage current through the gate exceeds 1µA. Figure 7

Conclusions
Bias temperature instability measurements have been performed on SiC Planar and Trench MOSFETs. Pulsed V GS measurements are performed over a frequency range between 1 Hz and 100 kHz. For the pulsed stresses, different turn-OFF V GS voltages (0 V, -3 V and -5 V) are tested so as to investigate the impact on overall V TH shift. The results show an increase in the measured V TH shift with frequency up to 1 kHz with V TH shift becoming independent of frequency after 1 kHz. This was the case for both the Planar and Trench MOSFETs. When V GS-OFF = -5 V is used in the pulsed stress test, there is an NBTI problem with a net negative shift in V TH . This is because hole trapping/electron release occurs faster at V GS-OFF = -5 V and dominates the overall V TH shift. When V GS-OFF =-3 V, the net V TH shift is close to zero. For the pulsed V GS stresses with V GS-OFF = -5 V, as the junction temperature is increased to 150°C, the magnitude of the V TH shifts increases thereby causing more NBTI. When accelerated stress tests are performed with V GS = 30 V, the V TH shift increases with the Trench MOSFET more than the Planar MOSFET and the recovery occurs with longer time constants. Similar measurements were performed with silicon MOSFETs which showed negligible shifting thereby indicating that BTI remains present in SiC MOSFETs to a much larger extent compared to silicon devices.