Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations

We investigated oxide and interface defects of lateral 4H-SiC MOSFETs through capacitance-voltage (C-V) and conductance-voltage (G-V) characterization at various frequencies and temperatures. By employing consecutive up and down sweeps of the gate voltage at three different temperatures, we experimentally characterized the hysteresis width as the difference between up and down sweeps in the depletion to accumulation (d-a) and depletion to inversion (d-i) regions. We observed an increase in the hysteresis width with decreasing temperature. Although the hysteresis width is not affected by the small-signal frequency, at the same time, increasing the frequency leads to a strong stretch-out effect, especially in the d-i region.Our measurement results indicate that the hysteresis deformation of the C-V curves is dominated by three different trap types. First, interface acceptor-like defects located close to the conduction band can follow the small-signal frequency. Slower acceptor-like border traps with trap levels both close to the conduction band and in the middle of the band gap are however responsible for the increase of trapped negative charge with increasing gate voltage. Finally, we assume the presence of a fixed positive charge.


Introduction
4H-SiC MOSFETs are a promising technology for high power electronics [1]. However, silicon dioxide (SiO 2 ) on a Si-face SiC surface still remains a major research topic due to the high defect density compared to the SiO 2 /Si interface [2][3][4][5][6][7][8][9][10][11][12][13]. This is of particular concern because electrically active border and interface defects can not only affect the reliability of the device itself but also the operation of the application circuit [14]. Understanding the origin and influence of these different types of defects will help to reduce the defect density and increase device reliability. In this context, technology computer aided design (TCAD) can be a powerful tool to analyze the data from characterization measurements. Recently, some researchers have evaluated the influence of the interface traps on capacitance-voltage (C-V) curves by using Shockley-Read-Hall (SRH) theory [15][16][17][18][19]. In [15], the trapping behavior of interface and near-interface traps was simulated for MOS capacitors by employing SRH, trap-assisted tunneling and Frenkel-Poole models. The authors implemented both deep and shallow oxide traps to describe the hysteresis and the flat-band voltage shift increase with temperature. Furthermore, Marescra et al. [17] have not only shown that fixed positive charge influences the C-V curve, they also investigated the impact of variations in the capture cross section on the hysteresis effect. It was demonstrated that traps close to the valence or conduction bands are fast, while those close to the mid bandgap are slow. Despite all these efforts to improve the understanding of C-V measurements in SiC devices, a complete simulation of a lateral 4H-SiC MOSFET calibrated and validated with measurement data at different small-signal frequencies and temperatures has not been performed yet.
In this work, we present such a TCAD [20] model including Shockley-Read-Hall (SRH) theory and the non-radiative multi-phonon (NMP) theory [21] for the description of charge transfer reactions associated with defects at the interface and in the oxide, respectively. The resulting model has been calibrated with C-V curves from impedance measurements at different temperatures and frequencies.

Devices and Experiment
We used lateral 4H-SiC nMOSFETs with a n + poly silicon gate. We assume an oxide thickness of 68 nm and a gate length of 7.5 µm, see Fig.1, left. This oxide layer was formed on the Si-face substrate by chemical vapor deposition. For C-V and conductance-voltage (G-V) curve measurements, the small-signal method was used. For equivalent circuit capacitance and conductance were connected in parallel mode. Both the sinusoidal small-signal for each bias step and the gate voltage up and down sweeps were implemented for investigating the trapping dynamics, see Fig. 1, right [17,24]. The gate voltage V gs is swept up and down within the range of −30 V to 30 V at a sweep rate of 2.0 V s −1 , see Fig. 1, right. The amplitude of the small-signal was 50 mV with a frequency between 4 kHz and 1024 kHz. The time step for each gate bias was 0.13 s and the delay between up and down sweep was 12 ms. The hysteresis width was extracted for operating temperatures of 300 K, 373 K, and 448 K.   Capacitance Capacitance

The Modeling Framework
To explain the C-V curves at various frequencies from Fig.2a,c we used an exponential distribution of fast acceptor-like interface defects located close to the conduction band (see Fig. 3) [15][16][17][18][19]. Due to their small capture (τ c ) and emission (τ e ) time constants over a large bias range, charge trapping and detrapping can follow the small-signal modulation. The interface traps that capture electrons become electrically active and are directly integrated with the mobility degradation model. In a simplified way the effective mobility is proportional to where µ C is the Coulomb component of mobility model. By fitting the measured and simulated curves we extract these parameters, which can reproduce the measured C-V curves with high accuracy. In our work we used µ 0 = 18 cm 2 V −1 s −1 , α = −9.2, and D it (T ) is the temperature-dependent interface charge density [20]. The capture cross section for electrons and holes was σ = 10 −15 cm −2 [20]. Our measurements show a negligible influence of donor-like traps which are located close to the valence band and which are hence not considered in the simulation, see Fig.2. Furthermore, we introduced a Gaussian distribution of slower acceptor-like border traps D 2 ox close to the SiO 2 /SiC interface, which turned out to be located around the middle of the 4H-SiC band gap. We further calculated the capture and emission times of the involved border traps by using the NMP model [21]. In this model, the asymmetry of barriers for the forward and backward processes leads to differences in charge capture and emission times. These barriers are determined by the relaxation energy S = 4.0 ± 0.1 eV and the parabolic curvature ratio R = 2.0 ± 0.1. The bias dependent asymmetry of capture and emission times influences the hysteresis width from the depletion to the accumulation region. Also, we assume a second Gaussian distribution of slow acceptor-like border traps D 1 ox with a lower concentration which is energetically located close to the 4H-SiC conduction band. The relaxation energy of D 1 ox is S = 0.1 ± 0.01 eV, and the parabolic curvature ratio is R = 1.0 ± 0.01. These defects affect the hysteresis width of the depletion to the inversion region [25]. The high concentration of acceptor-like traps results in a severe positive voltage shift towards higher V gs . Hence, we introduced fixed positive traps N fix it to compensate for such a large ∆V shift. The parameters for the models are summarized in Table 1. The effective gate voltage shift for the up and down sweeps was calculated by using Eq. 1.
Where V ideal is the ideal C-V curve without any defects, ∆V it is a shift caused by the interface traps, ∆V 1 ox is shift caused by slow traps which are located close to the conduction band and depending on sweep rate (SR) and temperature, ∆V 2 ox is shift caused by slow traps which are located close to mid gap and V fix is fixed positive traps.

Results and Discussions
Based on our measurement results and the modeling framework we investigated the behavior of the C-V curves at various temperatures and frequencies. Fig.4, right shows the comparison of the hysteresis width between measured and simulated C-V at 4 kHz and 300 K. By increasing the gate voltage we scan the 4H-SiC band gap and see how traps with different energies influence the C-V curve. Depending on their energy position relative to the Fermi level traps capture electrons and store them at different gate biases, thus two different hysteresis widths at the d-i and d-a regions occurred. In detail, the time evaluation of the slow acceptor-like traps D 2 ox indicates that by increasing the gate voltage, the emission times become longer than the capture times and partly even exceed the sweep time (ST), which means that some of the defects keep their charge state during the entire bias sweep, see at Fig. 4, left. Therefore, these slow defects appear to be responsible for the hysteresis width ∆V d−a H . Nevertheless, an increasing temperature decreases the hysteresis width, and ∆V H from depletion to accumulation (d-a) is 10 times higher than from depletion to inversion (d-i). However, in case the emission time remains higher than the ST, we do not observe a strong temperature dependence of ∆V d−i H . This is because the down sweep time is enough to release electrons due to their fast time constants. Otherwise, at low temperature, during the up voltage sweep electrons are captured due to the emission time being larger than the capture time τ e ≥ τ c , and traps become negatively charged. As a result, ∆V is shifted towards positive gate voltages, see  The voltage shift ∆V strongly depends on temperature and frequency, especially from depletion to the inversion region, see Fig. 5, left. With the increasing temperature, the capture and emission rates increase as well (or at the same time τ e < τ c ) which leads to defect neutralization and thus a decreasing voltage shift. The frequency dependence of C-V curve distortion indicates interface traps. Fig. 5, right shows that the fixed positive defects deviate the C-V measurement from ideal, and shift it towards lower gate voltages by 6 V at all frequencies (∆V fix ). At the same time, the shape of the ideal C-V curve is close to the measurement at low frequency and is not affected by sweep rates and higher frequencies. The fast interface traps D it can follow the small-signal frequency due to capture time being smaller than emission time. Therefore, a lot of interface traps are charged and we observed the distortion at C-V curves under high frequency, see Fig.5, right. In addition, Fig. 6 depicts the extracted measured and simulated dependencies of the hysteresis widths, voltage shifts, and capacitance swings. The strong frequency and temperature dependence from depletion to inversion confirms the presence of interface defects, see Fig. 6, middle, right. The hysteresis width in the depletion to inversion region is narrow due to low trap concentration D 1 ox .

Summary
In this work, we have presented a physical-based modeling approach to calculate the temperature activation of the hysteresis width and voltage shift of C-V curves of lateral 4H-SiC MOSFETs. We show that these behaviors are due to the charging and discharging kinetics of slow border traps in the oxide. The hysteresis widths of depletion to accumulation and from depletion to inversion region are caused by an asymmetry of the capture and emission times. These widths depend on temperature and sweep parameters but do not depend on the frequencies. In addition to slow border traps, the fast interface traps are responsible for the distortion of the C-V curves at various frequencies. Although the distribution of defect states is probably more complex than the used distribution in our simulation, our approach can explain the charge trapping dynamics and the general behavior of lateral 4H-SiC MOSFETs.