A Scalable SPICE Electrothermal Compact Model for SiC MOSFETs: A Comparative Study between the LEVEL-3 and the BSIM

In this paper, two implementations of a SPICE-based compact model for SiC MOSFETs are presented. The two versions rely on widely adopted LEVEL-3 and BSIM 4.6.1 models, respectively. The paper discusses the feasibility of adopting these two models for the description of SiC power MOSFETs. Furthermore, after calibrating the DC characteristics on target experimental data coming from 1.7 kV-60 A MOSFETs, a comparison between the accuracy of the two is presented.


Introduction
Compact modeling is a major field of research for the semiconductor industry and Simulation Program with Integrated Circuit Emphasis (best known as SPICE-like simulators) represent a fundamental tool for the modern circuit development. As it stands clear from the SPICE abbreviation, circuit simulation historically started to simplify the process IC design, but its importance rapidly extended into other areas of electronics, such as, analog circuit design, radio Frequency and power electronics. An acknowledgment of the significance of compact modeling for the power electronic world can be based upon the observation that most device manufacturers frequently release compact models along with their new products. Among all the SiC-based power devices, the MOSFET (in all its possible implementations) is probably the one that received the greatest attention from both research institutes and enterprises. The technological maturity of SiC MOSFETs gradually improved, during the last 20 years and, despite lower short circuit robustness, some devices also feature an inherently safe failure type [1], [2]. Therefore, the implementation of switching converters relying on both discrete SiC MOSFETs and power modules of various voltage ratings (from 650 V to 3.3 kV) remarkably increased in different market segments [3]. At the same time, there has been a higher demand for SiC MOSFETs compact models that are satisfactorily accurate and fast to allow a reliable validation of the design of complex converter machines. While device manufacturers usually provide compact models to allow the verification of their products, such models present several limitations. Some of them are based on polynomial fitting functions [4], with consequent possible inaccuracies when stimulated with electrical and thermal conditions exceeding those in which the model was tested. Furthermore, vendors encrypt [5] their model to protect the intellectual property, so not allowing to vary their internal parameters. In the last years, several examples of models for SiC power MOSFETs have been proposed in the literature. Good summaries can be found in [6] - [8]. The aim of this paper is that of presenting a SPICE-compatible model for SiC power MOSFETs that is based on a low number of parameters. The model is entirely based on SPICE standard components (i.e., that can be found in most SPICE versions and releases), thus making it compatible with any SPICE-like circuit simulator. Two versions of the model are presented and their static performances are validated on 1.7 kV-60 A-rated devices.

Implementation of the SiC MOSFET Compact Model
Introduction to the Modeling Technique. The compact electrothermal model described in this work is a variation of the one presented in [9], which has been previously tested on 1.2 kV-and 3.3 kVrated devices [10] - [12], but it relies on a much smaller set of parameters. Fig 1a represents the schematic cross-section of a planar vertical diffused SiC MOSFET (VD-MOSFET). In it, several parasitic sub-structures can be identified, i.e., regions where the arrangement of the materials resembles that of other components (e.g., capacitors, resistors, and inductors) or semiconductor devices (e.g., diodes, BJTs, and JFETs). Therefore, the device under test (DUT) is modelled as a subcircuit where such simpler components are interconnected so that their concurrent operation describes the behavior of the DUT. Such an approach is oftentimes referred to as macro-modeling. The channel layer forming in the p-doped well under the gate oxide is described through a standard SPICE MOSFET component, labelled as MCH. In [9], such a MOSFET was implemented through a LEVEL 1 MOSFET connected to further behavioral current sources to the take into account additional phenomena (such as, the mobility degradation due to high horizontal and vertical electric fields). In this paper, two alternative models are considered for the description of MCH: a LEVEL-3 and a BSIM 4.6.1. These are widely adopted models and implemented in most SPICE versions. A comparison of their DC performance is provided in the following subsections. Within the semiconductor cross-section, the JFET region is the one extending between two pimplantations and has a significant impact on the on-state resistance. When the drain potential is higher than the source potential, the pn junction formed by the body and the epilayer is reversely biased. This causes the space charge region to expand more in the n-doped region than in the p-doped one (Fig 2) due to the lower doping concentration of the epi-layer. The moving boundary of the depleted layer pinches the current path and thus modulates the overall on-state resistance. In [9], such a phenomenon was formerly described by a voltage-dependent resistor based on a behavioral function. Here, a standard SPICE JFET (JRJ) models the accumulation and JFET regions. Replacing the resistor with a JFET reduces the number of fitting parameters, improves convergence, and strengthen the physic foundation of the model. The compact model is implemented as a SPICE subcircuit, a schematic of which is given in Fig. 1b.
The terminals ΔT and PD represent the temperature increment and the power dissipation, respectively, according to the temperature equivalent Ohm's law and enable the electrothermal feedback by connecting the model to a proper electrothermal network [13]. The behavior of the JFET region was characterized through TCAD simulations conducted on a reference structure [1] where a highly doped N++ layer (dummy channel) is added beneath the gate oxide. In this way, the source terminal acts as the anode-side contact of the parasitic JFET, thus allowing to isolate the impact of the JFET region on the total on-state resistance by suppressing the contributions given by the accumulation and channel regions. Fig. 2 reports the extension of the

Description of Channel MOSFET with LEVEL-3 and BSIM MODEL.
Both the LEVEL-3 model and the BSIM feature a vast number of parameters. Specifically, the LEVEL-3 relies on 87 parameters, while the equations of the BSIM 4.6.1 are based on 300 parameters. Such a high number of parameters is necessary to take into account all the effects governing the behavior of very short-channel integrated MOSFETs like the ones adopted in the digital industry. However, it is interesting to understand if a reasonably small set of parameters is sufficient to describe the DC behavior of SiC power MOSFETs. In this paper, 7 and 11 featuring in the DC-equations of the LEVEL-3 and BSIM were considered, respectively. On the other hand, 3 parameters were considered to describe the JFET. Despite being much smaller than the original number of parameters, their manual tuning is not a trivial task since they often mutually affect the DC characteristics. Therefore, a MATLAB graphical user interface (Fig. 3) was developed to assist the model calibration. After an initial selection of the main parameters, the fine tuning is performed through automatic optimization cycle, a flowchart of which is reported in Fig .4. Comparison of DC Accuracy. The model was calibrated on 1.7 kV/60 A-rated SiC MOSFETs. The target data for the optimization routine are the isothermal static current-voltage characteristics (ID -VGS and ID -VDS), both at 25 °C and at 125 °C. These were measured through a pulsed curve tracer developed in-house. The overlap with the experimental DC characteristics (Fig. 5a-b) highlights that excellent agreement was achieved at room temperature by the model where MCH is implemented as a LEVEL-3. Subsequently, the optimization procedure was repeated to evaluate the temperature coefficients of the static parameters. The comparison reported in Figs. 5a and 5c shows that the model can accurately reproduce the DC characteristics also at 400 K, with only a slight deviation in the ID-VGS curve at high VGS. Therefore, the selected subset of parameters of the LEVEL-3 MOSFET and LEVEL-1 JFET allows to provide a good description of the ID-VDS and ID-VGS of the tested SiC power MOSFET. A comparison between the experimental and DC characteristics simulated when MCH is implemented with BSIM 4.6.1 is reported Fig. 6. In general, the agreement between the simulated measured data is satisfactory, However, the simulated curves deviate from the measured ones at high VGS values. On the other hand, it is worth specifying that, although both models never encountered convergence issues during the calibration routine, the model implemented with the BSIM always gave curves with smooth transitions between the various regions. On the other hand, the model implemented via the LEVEL-3 provided characteristics with sharp variations when the parameters were ill-selected. It is therefor worth exploring if adopting a relatively bigger set of parameters of the BSIM can provide better accuracy.

Summary
In this manuscript, two implementations of a SPICE-based compact model for SiC MOSFETs have been presented: one based on the LEVEL-3 MOSFET model, the other relying on the BSIM 4.6.1. to assist the calibration of the DC characteristics to the experimental data of a 1.7 kV-60 A-rated SiC MOSFET, a graphical user interface and a semi-automated calibration procedure have been developed. The comparison between the simulated and measured characteristics has shown that the LEVEL-3-based model can provide adequate accuracy. The BSIM-based model provided lower accuracy yet giving smoother characteristics. Further investigation are needed to understand whether a wider set of parameters can improve the accuracy obtained by the latter model.