Power Cycling on Lateral GaN and β-Ga2O3 Transistors

The load cycling capability of novel power semiconductors is an important aspect when estimating their lifetime in field service. The Power Cycling Test (PCT) is the standard test to evaluate the lifetime of a semiconductor device under thermo-mechanical stress. PCTs are typically performed at temperature swings (ΔT) much higher than common operating conditions, to obtain results within a reasonable time. In this work, the PCT capability of gallium nitride (GaN) and gallium oxide (Ga2O3) lateral transistors is investigated. The GaN devices were tested in two groups with different ΔT. The temperature of the devices was monitored using two different temperature sensitive electrical parameters (TSEPs) and the accuracy of both methods was evaluated by comparing the results with the temperature, monitored by using an infrared (IR) camera. For Ga2O3 devices, no data on potential TSEP exists so far, thus, the typical TSEP for silicon (Si), silicon carbide (SiC) and GaN were investigated for their applicability to Ga2O3 devices. While a PCT was conducted on the devices, the temperature was also monitored using an IR camera. The results of the comparison of TSEP and IR camera data showed, that the accuracy of the TSEP for GaN matched either the temperature of the hottest spot on the chip (VDS method), or the average chip temperature (VGS method). For the Ga2O3 devices no suitable TSEP could be obtained and only the IR camera was used for the temperature measurement. It revealed a very uneven temperature and thus, current distribution on the chip. Furthermore, both GaN and Ga2O3 devices exhibit an outstanding power cycling capability with no failure after completing several millions of cycles. Considering the difference in Young’s Modulus of Si, GaN and Ga2O3, the PCT performance of GaN on silicon devices and Ga2O3 devices should be inferior to silicon devices. Thus, both device types, the GaN transistors and the Ga2O3 transistors, showed a PCT capability much higher than expected.


Introduction
During their lifetime, semiconductor devices are exposed to frequent temperature cycles. These cycles lead to thermo-mechanical stress at the interfaces of the different materials or inside the materials. This stress can result in die-attach degradation or bond wire fatigue, which leads to an increase in thermal or electrical resistance. Such failures are investigated by power cycling tests (PCT). For novel semiconductor devices based on gallium, such as gallium nitride (GaN) and gallium oxide (β-Ga2O3), the PCT performance should be inferior to silicon (Si) devices, based on the Young's Modulus (Si: EY,Si = 130-190 GPa [1], GaN: EY,GaN = 210-405 GPa [2], β-Ga2O3: EY,Ga2O3 = 245-261 GPa [3]). However, while there are no publications for PCTs on Ga2O3 devices yet, recent publication for GaN devices showed, that they are outperforming silicon devices by orders of magnitude [4]. The root cause of this discrepancy was investigated in this work.
The temperature swing ΔT is the main acceleration factor during the PCT and hence, an accurate and reliable measurement of ΔT is essential to be able to use lifetime models to predict the behaviour of the devices under normal conditions and predict the service life of devices. Therefore, applying a suitable temperature sensitive electrical parameter (TSEP) is crucial to provide a precise junction temperature estimation. Several parameters were investigated as possible TSEPs for SiC devices, including the voltage drop of the body diode VSD, the on-state resistance RDS,on and the threshold voltage Vth [5]. For GaN devices, the drain-source voltage VDS and the gate-source voltage VGS were investigated so far [4]. In this work, the TSEPs VDS and VGS are evaluated for GaN devices, while for the Ga2O3 device VDS and Vth are investigated as possible TSEPs. Furthermore, the PCT capability of the tested devices is evaluated.

Devices Under Test and Test Setup
As devices under test (DUTs), commercially available discrete GaN Gate Injection Transistors (GIT) and research level chips of β-Ga2O3 normally-on MOSFETs on test substrates from Ferdinand-Braun-Institut, Berlin [6], were used. Both device types are lateral devices with gold bond wires, bonded on the edges of the chips.

PCT on GaN
For all PCT tests conducted on the GaN devices, the DUTs were kept in on state over the course of the tests with continuous gate current (IGSmeas). Furthermore, the drain measurement current (IDSmeas) was applied continuously. The switching of the drain load current (Iload) and thus the controlling of the heating (ton) and cooling (toff) phase was done by using auxiliary switches Two PCTs with 4 GaN-GIT each were performed with slightly different parameters. The temperature swing of ΔT was determined in each run using the TSEPs VDS and VGS. The first run was performed with Tmin = 20°C and ΔT = 60 K, ton = 0.5 s, toff = 1 s, IGSmeas = 18 mA, IDSmeas = 500 mA and Iload = 20.9 A. After more than 4.6 Mcyc without any visible degradation of the components, the test was terminated.
For the preparation of the second run, a set of fresh DUTs was parameterised at IDSmeas = 500 mA and a maximum allowed gate current of IGSmeas = 20 mA to achieve the maximum possible ΔT swing. Unfortunately, the DUTs become thermally unstable at very small current increases of the load current, although the water-cooled heat sink is operating at a controlled cooling temperature of 20°C. Figure 1 shows VDSon curves at the end of the on-phase at load current between 25.7 A and 26.8 A.
To avoid thermal runway and thus an early destruction of the device, the load current was limited to 25.7 A during the second test run.

Functional Materials and Materials Reliability
The second run with Tmin = 20°C, ΔT = 95 K, ton = 0.5 s, toff = 1 s, IGS,meas =20 mA, IDSmeas = 500 mA and Iload = 25.7 A was terminated after more than 7.3 Mcyc without any visible degradation of the DUTs. Normalised characteristics of VDS/GS, and ΔTvj of DUT#1 are shown in Figure 2. The curves are normalised to their initial mean values obtained between 20 kcyc and 50 kcyc. Over the course of the test, a marginal increase of the ΔTvj was observed. Additionally, a ΔTvj offset was visible upon resumption of the test after interruptions at 0.6 Mcyc and 3.6 Mcyc.

Temperature Sensitive Parameter for GaN
In addition to the VDS as TSEP, the VGS (diode) [9] [10] can be used as TSEP for the GaN-GIT. A direct comparison of the VDS and VGS methods using the calibration curves showed that the spread of the VGS curves among the DUTs was larger compared to the VDS curves ( Figure 3). This is clearly shown by the offset-compensated zoom part in Figure 3 in the range of 145°C and 155°C degrees of Tvj. The VGS TSEP offers a better resolution of − 2.6 mV/K vs 0.2 mV/K with the VDS TSEP.
After two test runs without failures, three fresh DUTs (DUT1IR, DUT2IR and DUT3IR, Figure 3) were calibrated and prepared for TSEP validation via an IR camera. The DUTs were decapsulated down to the chip surface and then the chip surface was coated with a thermographic paint (Lab IR Paint, HERP-HAT-MWIR-BK-11) to achieve a constant emissivity. In order to investigate the repeatability, multiple measurements with the same test conditions were performed. At first, measurement series I was conducted at the same conditions as in the second PCT test run with IGSmeas = 20 mA, IDSmeas = 500mA and Iload = 25.7 A resulting in Tvj,max = 139°C. Furthermore, measurements at higher Tvj,max (≈ 154°C, series II and ≈ 167°C, series III, all temperature values of the VGS measurement) were performed.  The measurements via TSEP, shown in Figure 4, confirm that the VGS method features a smaller noise level than the VDS method, due to the better resolution. The associated box plots are shown as insets in Figure 4. The temperature values in the box plot are extrapolated to the maximum temperature at turn-off, since the temperature estimation with TSEPs starts with a delay of 30 µs after turn off. The box plots suggest, that the VGS method also provide a more stable temperature estimation. On the other hand, the variation among the DUTs is much higher for the VGS method due to the variance in Vth (see Figure 3) and hence, the VGS calibration has to be performed for each DUT individually.
Another important property is the accuracy of the TSEP. Figure 5 shows a validation of Tvj using the IR camera. The top-left image shows a typical decapsulated device without the thermographic paint. The two bottom graphs show the thermographic image at the maximum temperature during a single power cycle. Furthermore, the temperature distribution of the chip, the respective temperature profiles of the areas of interest and the associated transient curves (right graph) are shown.
The camera data revealed, that the temperature swing ΔT measured by the VDS method corresponds well with the highest temperature of the chip, which is a spot on the active area. The VGS method matches the average temperature of the active area (see Table I). However, since the chip is bonded on the edge and not on the chip's active area, the ΔT at the possible point of failures, i.e. bond feet, was significantly lower (by around 30 K) than the temperature estimated by the TSEP. This can at least partially explain the significantly better PCT performance.

Temperature Sensitive Parameter for Ga 2 O 3
In preparation of the PCT on the Ga2O3 chip, measurements were carried out to find a suitable temperature sensitive parameter to determine the (junction) temperature of the chip. Since VDS, VGS and Vth are frequently used TSEPs for other device topologies and materials, those methods were considered and investigated regarding their applicability for Ga2O3.

Functional Materials and Materials Reliability
For this purpose, the quasi-static output characteristics were measured for different temperatures between 23°C and 120°C (105°C for threshold voltage measurements) and gate voltages VGS between -20 V and -10 V. (see Figure 6 for the temperature dependence of the ID-VDS curve for a gate voltage of VGS = -14 V and Figure 7 for the temperature dependence of the threshold voltage measurement).  Figure 8, the temperature dependence of the drain current ID for a fixed drain source voltage exhibited a linear behaviour. The temperature dependence of Vth, on the other hand, showed a non-linear behaviour (Figure 9). To investigate the stability of the measurement methods, which is required for the usage of the parameter as TSEP, all measurements were carried out twice. The comparison of the first and the second measurements of the output characteristics as well as the threshold voltage revealed a highly "dynamic" behaviour ( Figure 10 and Figure 11). There was a large drift in the threshold voltage, which also showed a strong nonlinear behaviour. The shift in threshold voltage was observed in lateral Ga2O3 in several publications [7] [8] [11] and was found to be due to charge trapping taking place in oxide border traps [11]. Due to this unstable behaviour, none of the investigated TSEPs were suitable to provide a stable and accurate temperature estimation and hence, the temperature during the power cycling test was measured exclusively by thermography.

PCT on Ga 2 O 3
One PCT on a β-Ga2O3 transistor was performed with Tmin = 14°C, ΔT = 64 K, and Iload = 0.46 A. The on-time was ton = 3 s and the off-time was toff = 6 s. The Ga2O3 chip was mounted on a watercooled heat sink to provide a stable cooling temperature and to avoid thermal runaway. This was necessary, as the Ga2O3 sample showed a similar thermally unstable behaviour at very small current increases as observed in the tested GaN devices, which limited the achievable temperature swing.
The sample was coated with the thermographic paint, also used for the GaN test, to provide a homogenous emissivity and allow accurate temperature readings by thermography. The test was carried out at a gate voltage of VGS = 0V and the load current was controlled using auxiliary switches. The test is still ongoing and has already completed more than 2.2 Mcyc without failure. 162 Functional Materials and Materials Reliability Figure 12 shows the VDS (mean value) and chip temperature readings of the power cycling test. It is visible that both, VDS and ΔT exhibit a decrease over the course of the PCT, likely caused by a shift of the electrical characteristics of the chip, which were observed to be instable (see Figure 10).  Figure 13 depicts the temperature measurement of the Ga2O3 PCT. The measurement illustrates, that the temperature of the bond wires (green and orange lines) was about 10 K lower than the average temperature of the chip (pink box and lines in graph) and significantly lower (by about 40 K) than the hottest spot on the chip's active area. This observation is similar to the measurements carried out on the GaN devices.

Summary and Conclusion
In this work, the PCT capability and possible TSEPs for GaN and Ga2O3 devices were investigated. Both GaN-GIT and Ga2O3 MOSFETs were lateral devices with gold bonds outside of the chip's active area. The results show, that for GaN, suitable TSEPs with a stable temperature estimation could be determined, while for the Ga2O3 devices, all investigated TSEPs are inapplicable, due to their instabilities.
Furthermore, the temperature measurements for the GaN devices show that the junction temperature estimation by VDS as TSEP corresponds well to the hottest spot on the chip, whereas the temperature on the possible point of failure, the bond feet, is severely overestimated (by around 30 K). This is a result of the lateral topology of the device and hence, the temperature swing at the bond feet of the Ga2O3 devices is also significantly lower than the average chip temperature. Due to their unstable behaviour, the GaN and Ga2O3 devices showed thermal runaway already at very small current increases, which limited the achievable maximum temperature swing for both devices.
In the PCT, the GaN devices passed 4.6 and 7.3 Mcyc, respectively, and the Ga2O3 devices passed 2.2 Mcyc without any sign of degradation. These values are at least an order of magnitude higher than expected (ca. 100 kcyc based on silicon parameters) and cannot be explained by thermo-mechanical properties alone. In fact, the temperature estimation based on both, VDS and VGS, delivers a junction temperature with a strong emphasis on high temperature regions (for the GaN devices). As a result of the thermal runaway, all tests were performed at comparatively low junction temperature swings and hence, even lower temperature swings at the possible point of failures. In combination with the difference in bonding technology this can explain at least partially the much better power cycling performance of lateral GaN and Ga2O3 devices compared to silicon.
However, since the measured ΔTvj is not a good predictor for ΔTPoF, neither the established lifetime models can be applied, nor the better power cycling performance translates necessarily into a longer service life. Additionally, the die attach has not limited the devices' lifetime in these tests, thus power cycling seems not to be lifetime limiting for this kind of devices. However, this might change with more aggressive designs, in particular when bonding on the active area to minimise the chip size and requires continuous verification.