Gate Dielectric Current Transport Mechanisms in N-SiC Metal Oxide Semiconductor Capacitor

In this work, the voltage and temperature behavior of gate leakage current transport in SiC/SiO2 metal oxide semiconductor (MOS) capacitor was investigated. The wide range of gate voltage from-50 to 50V and temperature from 300 to 400 K, respectively uses to study the gate current conduction mechanism. Two dominant gate leakage current transport modes in SiO2 during strong accumulation with the application of positive bias were caused by Fowler–Nordheim (FN) tunneling and Poole-Frenkel (PF) emission leakage conduction. For positively biased case, FN tunneling in the range of 30-40 V dominates the gate leakage current and Poole–Frenkel conduction attributed beyond 40 V.


Introduction
Owing to its wide bandgap physical properties, silicon carbide (SiC) is a promising semiconductor candidate for high voltage power device applications with an increased voltage and switching frequency operations compared to silicon [1,2]. However, SiC based metal oxide semiconductor power devices with thermally grown oxide suffer from low quality SiC/SiO2 interface, which results in low channel mobility and gate oxide reliabilities. Furthermore, this issue is more pronounced in trench MOSFETs as the oxidation growth rate depends on crystalline direction in SiC. Past works have indicated that the complex electrically active bulk and interface trap states in SiO2 sub-oxide and at SiC/SiO2 interface, respectively, play significant roles in carrier transport through the gate oxide resulting in the degradation of the oxide lifetime and threshold voltage instability [3,4].
Higher interface traps also affect other issues like long-term degradation of the gate dielectric and the eventual reliability of the ultra-high power (UHP) SiC transistor. Several process tuning have been used to lower the interface traps at the SiC/SiO2 interface [5,6]. Hence, the study of the gate leakage current transport in SiC/SiO2 MOS capacitor is of highly practical interests and relevance to understand the reliability and degradation of the gate oxide.
In this work, we explore the conduction mechanism of the gate leakage current in SiC/SiO2 capacitor using current-voltage (I-V) measurements over a wide temperature range from 300 to 400 K. We also discuss the dominant conduction candidates for the conduction mechanism.

Results and Discussion
The SiC/SiO2 MOS capacitors were fabricated on a 4⁰ off-cut (0001) Si-face of 4H-SiC with 10µm thick & N-doped (10 16 cm -3 ) homo-epilayer deposited on highly doped n-type substrate. Pregate surface cleaning was performed via RCA method followed by diluted hydrofluoric acid (DHF) dip. SiO2 layer with a thickness of 50 nm was grown via thermal oxidation at 1350 o C in O2 for 18 minutes, followed by post-oxidation anneal at 1300 o C in N2 and NO gas for 30 min. The key process flow is described in Fig.1. After oxidation, the grown oxide was characterized by transmission electron microscopy (TEM) measurements. A 200 nm thick aluminum metal was evaporated on the front side using a shadow mask to create top electrode of the MOS capacitor while blanket metal was deposited on the back surface of substrate to form back contact. To understand the conduction mechanism in this SiC/SiO2 MOS capacitor, we performed a temperature dependent characterization of IG from 300K to 400K as shown in Fig. 3(a)-3(b). Two distinct modes were identified in Fig. 3(a) -Region-I: temperature dependent IG variation is fairly weak at gate voltage range (30V< VG < 40V) and Region-II: IG variation with temperature is very strong at gate voltage range (VG ≥ ~42V). These IG-VG data in regions I & II were further analyzed   by replotting them into log(IG/VG 2 ) versus 1/VG and log(IG/VG) versus VG 1/2 , respectively, as shown in Fig. 4 (a) & 4(b). In Fig. 4(a), the region-I replotted results (30V< VG < 40V) clearly showed four straight overlapping lines with a common negative slope at different temperature over 30V< VG < 40V. The results indicated the dominant gate oxide conduction mechanism is due to the FN tunneling of surface electrons from the SiC layer quantum mechanically injected into SiO2 through the triangular energy barrier at the SiC/SiO2 interface [7]. In Fig. 4(a), the region-II replotted results (VG ≥ +42V) showed parallel upward shift of the four fitting curves corresponding to temperature increases from 300K to 400K which confirmed the thermally sensitive Poole-Frenkel "traps-hopping" events dominates the transport of thermal electrons in SiO2 [8,9].

Silicon Carbide MOSFETs and Special Materials
When the applied positive gate bias increases from 25V to 40V, the electrons from n-type epi SiC (doing concentration 1×10 16 /cm3) accumulate more at SiO2/SiC interface as a result the corresponding energy band shows more bending in Fig. 5(b). This concept is similar to the conduction mechanism of a MIM tunnel diode, in which the electrons from the metal can tunnel into the insulator film whereas hole injection probability is negligible [6]. Therefore, the conductive mechanism is dominated by FN tunneling in step (I) in Fig. 3(a). When the voltage is increased 40 to 50V as shown

Summary
In this work, we experimentally confirmed two dominant gate current transport mechanisms in 50nm thick SiO2 using a combination of SiC/SiO2 MOS capacitors and temperature dependent IG-VG analysis. The electrical characteristics over a wide temperature range from 300 to 400 K indicate that the gate leakage current flows as the sum of the FN and PF leakage currents. The outcome of this work is relevant for a better understanding of the gate oxide degradation mechanisms and the associated reliability qualification (TDDB, QBD) of SiC based ultra-high-voltage power transistor.