A Unique Failure Mode of SiC MOSFETs under Accelerated HTRB

Device lifetime under reverse bias conditions is an important reliability concern for SiC devices. Provided that the termination structure is well designed, device failure in the active cell is driven by gate oxide breakdown due to the high field in the semiconductor and gate dielectric. For planar MOSFETs, the largest field occurs in the JFET region [1,2]. Standard HTRB testing is insufficient to estimate failure rates under operating conditions and hence testing under accelerated off-state conditions (ALT-HTRB) is required. This paper provides data, statistical analysis, failure analysis and finally a Weibull statistics-based temperature, Vd and stress time dependent model.


Introduction
Device lifetime under reverse bias conditions is an important reliability concern for SiC devices.Provided that the termination structure is well designed, device failure in the active cell is driven by gate oxide breakdown due to the high field in the semiconductor and gate dielectric.For planar MOSFETs, the largest field occurs in the JFET region [1,2].Standard HTRB testing is insufficient to estimate failure rates under operating conditions and hence testing under accelerated off-state conditions (ALT-HTRB) is required.This paper provides data, statistical analysis, failure analysis and finally a Weibull statistics-based temperature, Vd and stress time dependent model.

Devices and Experimental Data
The devices used in this study are 16mΩ, 750V rated planar gate MOSFETs, packaged in TO-247.Devices are stressed in parallel under different Vd and temperature conditions as listed in Table 1.It takes ~2s to reach the desired Vd,.An additional 2s stabilization is used before any device measurement is performed.Sample size is 48 devices per stress condition.Although the voltage rating is 750V, the transistors are stressed at Vd ranging from 875V up to 950V, with Vg=0V.In agreement with [1], stress conditions are in the Vd range of 0.875 to 0.95% of the avalanche voltage.Table 1.Experimental matrix for the ALT-HTRB stress tests (Vg=0V).Fig. 1 shows typical off-state Id-Vd characteristics for two different temperatures.As from Vd~920V, Id at RT is larger than Id at T=175 o C. The breakdown of the devices (measured at 10mA) is ~1kV.Fig. 2 shows Ig and Id at the stress condition at the start of the stress.For each group, the devices with the highest Id fail first, indicating that Id is a good proxy for the probability of a device to fail under ALT-HTRB.For Ig, there is no distinction between failed and non-failed devices.1).
Fig. 3 plots the t63% derived from the Weibull statistics for all experiments using censoring for the non-failing devices and using the E-model for field acceleration [1].In line with the expectation from the drain leakage current (Fig. 1) and the observation that the failure mode is current driven (Fig. 2), there is a cross-over in tfail at Vd~920V.Using the field acceleration model of Fig. 3 (E-model) and assuming an Arrhenius temperature dependency, a lifetime contour map can be constructed for any given desired ppm level using the t63% failure times and an experimental Weibull slope of β=1.5.As an example, Fig. 4 shows the lifetime contour map at 100ppm.

Failure Analysis
Failure analysis is performed on 20 devices, from all groups of the experimental matrix.In all cases, the failure spot is in the active area, in the center of the hex cell of the JFET region, see Fig. 5.More specifically, the devices all fail as shown in Fig. 6 i.e. at one side of the hex cell only (red dots).If only the electric field in the SiC and/or SiO2 would be the driving factor, half of the population is expected to fail at the location of the green spots of Fig. 6.This unexpected anomaly can be explained by the anisotropy of the avalanche plasma, which moves faster along the c-plane [2] and the fact that the crystal has a 4 o offcut angle.Therefore, avalanche carriers generated at the p-body/n-epi junction at the location of the green arrows and dots in Fig. 6 will move under the p-body contact region where there is no gate oxide.In contrast, avalanche carriers generated at the location of the red arrows and dots will encounter the higher field in the JFET region and create electron/hole pairs.These hot holes can then cause SiO2 degradation and wear-out, ultimately leading to failure.This is another argument that the degradation of transistors under ALT-HTRB is driven by avalanche in the semiconductor and is dissimilar to gate oxide degradation during TDDB.Hence care should be taken on which field acceleration model to use.On two samples TEM was done, but no crystal defects were revealed in either sample, in agreement with [1] but in contrast to [3,4,5].Impact ionization occurs at the curvature of the p-body/n-epi (both at the red and green dots).The red dots represent the locations where the devices always fail (see Fig. 5).The green dots represent the locations where the devices never fail.Only for the red dots, avalanche carriers (generated at the pbody/n-epi junction) can reach the high field region in the JFET.This is because the impact ionization plasma preferentially moves along the c-plane, i.e. to the left of the wafer because of the 4 o offcut angle [3].Secondary hot holes are only generated if the plasma reaches the JFET high field area (red dots).
During stress, Ig and Id for each individual device is monitored.When either Ig or the Id reaches compliance at 100nA or 1mA, the device is reported as a "soft" or "hard" failure respectively.Figs.7 and 8 show the on-state and off-state characteristics of two typical "soft" and "hard" failed devices.Irrespective of "soft" or "hard" failure mode, the emmi spot is always in the center of the hex cell (as in Fig. 5).)."soft" failure when Ig_off reaches compliance (100nA), "hard" failure when Id_off reaches compliance (1mA).For the "soft" failing device the transistor is still working properly, with good on-state and off-state behavior (see also Fig. 8).For the "hard" failing device, transistor action is lost.

Parametric Degradation During Stress
During stress device parameters are measured in-situ.Up till failure, all prime device characteristics remain unchanged (Vth, Ron, Ig_on, Id_off, etc), except for Ig_off (measured at the stress condition) see Fig. 9. Ig_off drops due to the build-up of positive charge in the dielectric in the JFET region.The fact that the prime device parameters do not change with stress indicates that the degradation is not in the channel area of the transistor, but in the JFET area, in agreement with the model of Fig. 6.

ALT-HTRB versus Single Event Burn-out (SEB)
It is instructive to compare the magnitude of the failure rate of ALT-HTRB against other failure mechanisms that occur under reverse bias, more specifically single event burn-out (SEB) due to cosmic rays.Fig. 10 shows the extracted FIT rates for ALT-HTRB (calculated from the MTTF of the Weibull data), compared to SEB FIT rates (from neutron irradiation experiments).Fig. 10.SEB and ALT-HTRB FIT rates.For ALT-HTRB, the full lines correspond to the E-model (as per JEDEC JC70.2), whereas the dashed lines correspond to the 1/E model (which is in line with an avalanche model, since tfail~Javal -1 ~Jd -1 .exp(1/E).Up to Vrating, the FIT rate is determined by SEB, not ALT-HTRB.Although throughout the paper the E-model is used for field acceleration for ALT-HTRB (as per JEDEC JC70.2), it is instructive to also calculate the extrapolation for the 1/E model (dashed lines in Fig. 10).The 1/E model is more in line with an avalanche driven failure mode, since tfail~Javal -1 ~Jd -1 .exp(1/E)Up to Vrating, the FIT rate is determined by SEB and not by ALT-HTRB.

Conclusion
This paper provides evidence that the failure mode during ALT-HTRB is driven by avalanche driven hot holes, which is different from standard TDDB gate oxide degradation.Model extrapolation shows that below Vrating SEB dominates the FIT rate.In all of the failing devices that were submitted for failure analysis, no crystal defects were found to be the root cause of the failure.This finding is in agreement with [1] but in contrast to the findings of [3,4,5].

Fig. 1 .
Fig. 1.Id-Vd characteristics of SiC parts at Vg=0V, at T=25 o C and 175 o C. Vrating=750V, Vbd~1kV.The vertical red dashed line denotes the voltage rating of the devices.

Fig. 2 .
Fig. 2. InitialIg and Id at the stress condition for the devices under ALT-HTRB.Open symbols are the devices that fail during the test (see Table1).

Fig. 3 .
Fig. 3. t63% derived from the Weibull statistics of the tfail data, using the E-model.For Vd>920V, the tfail is lower at T=25 o C compared to T=175 o C, see also Figs 1 and 2.

Fig. 5 .
Fig. 5. Typical example of the failure location during ALT-HTRB (OBIRCH).The devices always fail in the center of the hex cell of the JFET region.

Fig. 6 .
Fig. 6.(a) cross section of the SiC crystal from the wafer flat.The grey regions denote the p-body areas, green is the n-epi/JFET region.The 4 o off-axis angle is towards the left side of the wafer when the flat is at the wafer bottom.(b) top view of the cell layout, with the wafer flat at the bottom.Impact ionization occurs at the curvature of the p-body/n-epi (both at the red and green dots).The red dots represent the locations where the devices always fail (see Fig.5).The green dots represent the locations where the devices never fail.Only for the red dots, avalanche carriers (generated at the pbody/n-epi junction) can reach the high field region in the JFET.This is because the impact ionization plasma preferentially moves along the c-plane, i.e. to the left of the wafer because of the 4 o offcut angle[3].Secondary hot holes are only generated if the plasma reaches the JFET high field area (red dots).

Fig. 9 .
Fig. 9. Parametric degradation of |Ig_off| during ALT-HTRB stress at Vg=0V, Vd=900V, T=25 o C. Ig_off measured at the stress condition of Vd=900V.Ig_off drops due to the build-up of positive charge in the gate dielectric during stress.