Investigations on 4H-SiC Low Voltage nMOSFETs with Thin Thermal SiO2/ Deposited Oxide Gate Dielectric

The poor quality of SiC/SiO2 interface significantly limits the channel mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation by NO has been adopted widely by manufactures because nitrogen may replace carbon in some chemical bond at the SiC/SiO2 interface. However, excessive nitridation is not desirable because of pronounced hole-trapping effects near the conduction band. As an alternative gate dielectric, thin SiO2/deposited oxide stack has been investigated in 4H-SiC lateral nMOSFETs. Overall performances were reviewed in aspects of transfer/gm/reverse characteristics, charge pumping method and TLP characteristics.


Introduction
Silicon Carbide has become an important electronic material due to the potential of SiC power devices to provide efficient energy distribution and management for applications such as smart grid and electric vehicles. Despite continuing advances in fabrication and design, the channel mobility limits the performance which is caused mainly by structural imperfections of dielectric layer as well as in the interface. Interstitial carbon clusters, Si and C vacancies in the SiC surface and most probably a high strain of interface atomic layers are responsible for the creation of electrically active traps [1][2]. The alternative dielectric to improve the channel performance using 50Å thermal SiO2/350Å deposited oxide has been analyzed through 4 terminals LV nMOSFETs and compared to nMOSFETs with 400Å thermal SiO2. The reliability concerns of each dielectric have been evaluated by ESD performance using TLP characteristics for future vehicles in real applications. Fig. 1(a) shows the cross-section of 4 terminals 40V nMOSFETs fabricated on 4H-SiC epilayers on n-type substrate. The gate last process is used wherein gate dielectrics are formed by annealing SiC and followed by post oxidation annealing. Transfer characteristics, gm and reverse characteristics depending on channel lengths are shown in Fig. 1(b) and 1(c) according to different dielectrics. VTH roll-off starts to be shown from LCH=3.0um in common, so we decided to proceed subsequent analysis focusing on LCH=4.0um / W=300um nMOSFETs to get rid of mis-alignment or short channel effects. Fig. 2(a) shows the calculated μFE from ID-VGS using the capacitance measured from MOS capacitors. μFE from 50Å thermal SiO2/350Å deposited oxide gate dielectric is increased by 10.6% compared to 400Å thermal SiO2 at the high field (=4.5MV/cm) and this result would be caused by less carbon clusters and Si vacancies which are generated during short-time oxidation. ID,Lin and ID,Sat curves are measured respectively to confirm Drain-Induced Barrier Lowering (DIBL) depending on each gate dielectric and very stable DIBL effects are observed without any subthreshold leakage as shown in Fig. 2(b) and 2(c).

Engineering Materials, Devices and Equipments
Interface state densities at each gate dielectric were characterized using charge pumping measurements as shown in Fig. 3. 10V pulse amplitude has been employed for the base voltage sweep. Average Dit can be extracted as a function of band-bending on the following equation; Avg. Dit=Icp/(qAf) where Icp is the charge pumping current, q is the electron charge, A is the channel area and f is the frequency. Approximately 50% higher Dit level is shown in the 50Å thermal SiO2/350Å deposited oxide gate dielectric than 400Å thermal SiO2 based on the result from charge pumping. gm in Fig. 1(c) also shows severe noises compared to Fig. 1(b) proving more Dit. Once you take a look at Fig. 3(b), the 2 nd peak is introduced in charge pumping plot. Amount of captured holes by hot hole injection are recombined with channel electrons and lead to additional substrate current making the 2 nd peak. The reason why higher Dit level is observed in 50Å thermal SiO2/350Å deposited oxide might be related to the insufficient oxidation time, so it would result in poor interface states than those of 400Å thermal SiO2. Nevertheless, μFE from 50Å thermal SiO2/350Å deposited oxide gate dielectric shows better than 400Å thermal SiO2 gate dielectric. When it comes to the channel mobility at least, surface roughness scattering that comes from carbon clusters generated during oxidation plays an important role than Dit does, especially under high fields [3].
Although SiC has been demonstrated with many superior properties like temperature tolerance, radiation hardness and thermal conductivity, the assessment of reliability regarding ESD performance could have a significant effect on the consideration of different gate dielectrics in nMOSFETs [5]. LV nMOSFETs operate properly showing on-state BV in Fig. 3(a) and 3(b) matches well with offstate BV in Fig. 1(b) and 1(c) respectively. However, 10V earlier dielectric damage on different VGS conditions tends to be shown at 50Å thermal SiO2/350Å deposited oxide gate dielectric. Therefore, the stacked gate dielectric needs to be revised by adopting more robust 50Å thermal SiO2 process which interfaces with SiC surface to improve the gate oxide integrity. There are no concerns on parasitic bipolar triggering or unwanted latch-up when considering dielectric breakdown voltage and rated currents of nMOSFETs after evaluating the effect of gate biasing on TLP characteristics.

Summary
The best way to reduce the channel resistance is to enhance the inversion carrier mobility by improving SiC/SiO2 interface quality. Currently, the channel mobility limits the performance mainly caused by structural imperfections of dielectric layer such as carbon interstitials, oxygen vacancies and carbon clusters at the SiC surface. Nitridation by NO gives a better result than that by N2O because N2O molecules are more stable at high temperature. Number of interface traps can be qualitatively scaled down with the amount of interfacial nitrogens [4] however, excessive nitridation is not desirable because of pronounced hole-trapping effects near the conduction band. The balance between oxidation and passivation is a critical point to get SiC surface passivated nicely. The gate last process wherein gate dielectrics are formed by annealing SiC is accompanied by oxidation of SiC

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Engineering Materials, Devices and Equipments surface inevitably and it leads to the degradation of interface properties through the introduction of carbon defects. The alternative gate dielectric by combining 50Å SiO2/350Å deposited oxide for minimizing oxidation of SiC has been analyzed and compared to 400Å SiO2 gate oxide in 4H-SiC LV nMOSFETs. 50% higher Dit level is observed in the stacked gate dielectric compared to 400Å SiO2 by using the charge pumping method, however μFE of the stacked gate dielectric is increased by 10.6% compared to that of 400Å SiO2 at the high field (=4.5MV/cm) due to less carbon clusters generated during short time oxidation. This means μSR affected by carbon clusters plays an important role than μC under the high electric field. Based on TLP characteristics, there are no concerns on parasitic bipolar triggering or latch-up considering dielectric BV and rated current of 4H-SiC LV nMOSFETs with the stacked gate dielectric.