Surface-Localized 15R Formation on 4H-SiC (0001) Si-Face by Laser Annealing for Power N-Type MOSFETs

A SiC MOSFET fabricated on a thin 15R-SiC layer on top of a 4H-SiC would benefit from both the higher inversion channel mobility of 15R-SiC and higher bulk mobility of 4H-SiC. In this work, a method based on Al implantation followed by UV laser annealing (UV-LA) to form 15R-SiC on 4H is shown. Evaluation of crystal quality and SiC polytype identification are performed by Raman spectroscopy. We show that UV-LA is able to grow 15R-SiC and cure the crystal damaged by ion implantation until a level close to the pristine substrate. This opens new perspectives for fabrication of SiC n-type MOSFETs.


Introduction
4H-SiC is the chosen SiC polytype for SiC MOSFETs because of its large bulk mobility, low anisotropy [1,2] and large substrates availability. However, the inversion layer electron mobility (μinv) on the (0001) plane Si-face channel in 4H-SiC MOSFET is so poor that it becomes a limiting factor of the on current [3]. Indeed, it has been shown that the high density of SiC-SiO2 interface states close to the conduction band leads to large inversion channel mobility degradations [4]. Assuming that SiC-SiO2 interface defect states, irrespective of the polytype, are pinned at the same energetical level with respect to the valence band edge, Schörner et al. claimed that the smaller bandgap of 15R could be the origin of the better measured μinv [5].
Therefore, the combination of a thin 15R-SiC layer on a 4H-SiC substrate would allow to benefit from both much greater μinv of 15R-SiC for the lateral channel and higher μbulk of 4H-SiC for the drift layer. However, while it is possible to grow 15R-SiC on the (0001 � ) C-face of 4H-SiC, it has never been achieved so far on (0001) Si-face nor on the (112 � 0) plane to the best of the authors' knowledge.
In this work, we report a way of forming a thin 15R-SiC layer on the (0001) Si-face of 4H-SiC by using ion implantation (I/I) and UV laser annealing (UV-LA).

Experimental
We implanted aluminum (Al) in the (0001) Si-face of standard N-doped 4H-SiC substrates at 500°C or 600°C to obtain a flat Al profile of about 5 × 10 19 at.cm -3 or 2 × 10 20 at.cm -3 over 200 nm from the surface. These "hot" I/I conditions were intentionally selected, assuming that the degree of crystal damage must be reasonable so that it can be fully cured by UV-LA. UV-LA were performed in N2-purged environment with various energy densities (ED) and dwell times in the range of a few µs to tens of µs. Samples were characterized by Secondary Ion Mass Spectrometry (SIMS), Raman spectroscopy and Transmission Electron Microscopy (TEM). Raman spectra were acquired from 100 cm -1 to 1800 cm -1 on a Renishaw inVia equipped with a 532 nm laser whose spectral resolution is 0.9 cm -1 .

Results and Discussion
As shown Fig. 1 for the targeted concentration of 5 × 10 19 at.cm -3 , the Al concentration at the plateau level is about 3 × 10 19 at.cm -3 , slightly lower than the target, and extends down to 200 nm in depth, as expected. Jia et al. showed that Raman spectroscopy can be used to evaluate crystal damage in I/I SiC. More precisely, the ratio between the E2(TO) (located at 778 cm -1 ) peak and the background level between the E2(TO) and LOPC (located at around 960 cm -1 ) peaks is an indicator of crystal damage [6]. Fig.  2 shows the Raman spectra taken on the pristine and as-I/I samples and normalized by the E2(TO) peak. As a consequence of the normalization, the higher the background level between E2(TO) and LOPC peaks, the higher the crystal damage is. The crystal damage is more pronounced for the most aggressive I/I condition (2 × 10 20 at.cm -3 at 500°C), whereas the intermediate conditions (2 × 10 20 at.cm -3 at 600°C and 5 × 10 19 at.cm -3 at 500°C) have a similar crystal damage level. The softest I/I condition (5 × 10 19 at.cm -3 at 600°C) leads to the least damaged crystal.

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Semiconductor Wafer Fabrication, Coatings and Tribology   3 shows the Raman spectra from 700 cm -1 to 1050 cm -1 taken on the pristine, as-I/I (5 × 10 19 at.cm -3 at 500°C), and UV laser annealed samples, clearly showing that the crystal damage is cured as the applied thermal budget increases from Process A to Process C. We highlight that the background levels of processes B and C are almost overlapping, which shows that crystal curing seems to saturate for thermal budgets between Process B and Process C. We can observe that the final level in between E2(TO) and LOPC peaks is still slightly higher than for the pristine sample, indicating that the crystal quality after UV-LA is not as good yet as the pristine substrate. Also, we observe that the peak at around 966 cm -1 , which possibly originates from specific crystal defects and which is clearly seen on the I/I sample, tends to disappear as the applied thermal budget increases.    5 shows Raman spectra from 100 cm -1 to 1050 cm -1 , where the progressive appearance with the increase of thermal budget of two other peaks, located at around 167 cm -1 and 331 cm -1 (see the inset), can be observed. These peaks are identified as the FTA and FLA peaks or 15R polytype of SiC [7]. The same progressive appearance of these peaks was observed for the other I/I conditions (data not shown). The fact that penetration depth at 532 nm in SiC is large (in the tens of µm range) makes difficult to decorrelate the contribution of the implanted layer from the un-implanted substrate. Moreover, E2(TO) peaks of both 4H-SiC and 15R-SiC are too close to each other to be distinguished. Therefore, the presence of FTA and FLA peaks of 15R-SiC clearly shows that some amount of 15R-SiC is regrown, and we can assume that it is regrown in the implanted layer, but we cannot quantitatively evaluate the proportion of 15R-SiC.

Conclusion
In summary, the formation of a thin 15R-SiC layer was experimentally demonstrated on the (0001) Si-face of the standard 4H-SiC substrate after Al I/I and UV-LA. Crystal curing by LA was also evidenced by Raman spectroscopy and TEM. Although the 15R-SiC covering ratio still needs to be measured, optimization of both I/I and LA conditions will be considered in a future work. This result opens new perspectives in terms of SiC n-type MOSFETs fabrication.