Reliability of SiC MOSFET Power Modules under Consecutive H3TRB and Power Cycling Stress

Power semiconductor modules are subject to both thermo-mechanical stress and electro-chemical stress during field operation. Usually, those stressors are investigated separately and possible interaction of both degradation mechanisms is neglected. In this work, the effect of combined thermo-mechanical and electro-chemical stress is investigated by means of consecutive H3TRB and PCT testing. One test group had been subjected to power cycling before the H3TRB test was performed, while another test group had been exposed to H3TRB stress before the power cycling test. As a reference, devices without preconditioning were tested in both, H3TRB and power cycling and are also used to compare the H3TRB and power cycling performance of the SiC devices to similar silicon devices. The results show, that the SiC devices feature a significantly better H3TRB performance than comparable silicon devices, but are inferior in terms of power cycling performance. Furthermore, the results for both test groups of the combined tests indicate that the failure modes for the previously stressed devices were the same as for the pristine devices and no impact of either preceding stress on the devices' lifetime could be observed. Therefore, the results of this work suggest no interaction between both stressors, at least not for the devices used for this investigation.


Introduction
When power semiconductors are used in harsh environments, they are exposed to electro-chemical stress caused by humidity from the environment [1] and thermo-mechanical stress caused by cyclic changes in power dissipation due to device operation and changing ambient temperatures [2]. At the same time, those applications, e.g. traction or wind power, often require a long service life with low failure rates. In order to ensure that the reliability demands are met, it is crucial to evaluate the impact of both stressors on the devices' reliability to estimate their service life under the respective conditions. Since this is usually investigated separately in High Humidity High Temperature Reverse Bias (H 3 TRB) tests for electro-chemical stress [3,4] and Power Cycling Tests (PCT) for thermo-mechanical stress [5,6], possible interaction of both stressors is not considered. While the electrical performance of SiC power devices make them very attractive for many applications and can drive electrification by increasing efficiency [7,8], the reliability of SiC devices and particularly the much shorter track record of field reliability is still a potential concern [9]. Due to the high critical field strengths of SiC and its more than 3x higher Young's modulus with respect to silicon, both electro-chemical and thermo-mechanical stress and their interaction can be potentially more critical for SiC compared to their silicon competitors, for which previous reports indicated some degree of interaction [10]. In this work, the reliability of SiC MOSFETs is investigated in terms of electro-chemical and thermomechanical stress and specifically, regarding a possible interaction of both stressors by consecutive PCT and H 3 TRB testing.  Fig. 1a. The chips were packaged in a base plate less module package with spring terminals (MiniSKiiP), depicted in Fig. 1b. The module consists of a DCB substrate with solder die-attach and silicone gel as filler material. For this investigation, a total of 24 SiC MOSFET modules of the same production lot were used.

Test Procedure
In order to investigate possible interactions of electro-chemical and thermo-mechanical degradation, both tests were performed consecutively on the same DUTs. The test sequence is illustrated in Fig. 2 and the test conditions for the H 3 TRB and PCT tests are summarised in table 1. First a PCT (run 1) was performed until end of life (EoL) of all 12 DUTs, to obtain the baseline power cycling capability of the package assembly under test. Afterwards, a second PCT (run 2) was performed until 50 % of the number of cycles to failure (N f) of run 1 was reached. As N f, the Weibull scale factor was considered (N f,63.2). In order to investigate a possible impact of preceding PCT stress on the H 3 TRB performance, and also assess whether the magnitude of the PCT stress has an impact, devices from PCT run 1 and run 2 were used for the subsequent H 3 TRB test. The test was performed on 4 devices of run 1 (split 1 "EoL"), 6 devices of run 2 (split 2 "Precon.") and 6 fresh devices as a reference (split 3 "REF").

H 3 TRB after PCT
The H 3 TRB test was performed with typical test conditions, i.e. at an ambient temperature of 85 °C and 85 % relative humidity and with a reverse bias voltage of 960 V, corresponding to 80 % of the devices' nominal blocking voltage. As a failure criterion, an increase in leakage current of one order of magnitude was used. DUTs, which had reached the failure criterion, were disconnected and removed from the test. The test was performed until all devices had failed at approximately 12,700 h (i.e. about 1.5 years of net testing time).

Failure Analysis
After the test, the DUTs were opened for optical failure analysis. Fig. 3 shows a microscope image of one DUT, which was subject to power cycling prior to the H 3 TRB test. It is visible, that the DUT exhibit a bond wire lift-off of the front most bond wire, which can be attributed to the preceding PCT. Furthermore, dendrites across the right side of the edge termination are visible, which show the degradation caused by the H 3 TRB test. A scanning electron microscope (SEM) image of part of the dendrites is shown in Fig. 4. An Energy Dispersive X-ray Spectroscopy (EDX) confirmed that the dendrites are composed of silver and grew on top of the passivation layer. Silver dendrites are common to occur during H 3 TRB stress and are a classical failure mechanism for silicon power semiconductors during H 3 TRB as well [11]. Other devices showed damage of the polyimide layer, previously reported in [4]. The degradation mechanisms were the same for all DUTs of all three H 3 TRB test splits and hence, no additional or other degradation mechanisms were triggered by the previous thermo-mechanical stress.

Statistical Analysis
The Weibull plots of the H 3 TRB test results are shown in Fig. 5, and the associated Weibull parameters are summarised in table 2. In comparison to the reference data for silicon [4], the Weibull scale factors are significantly higher for all test splits. While this indicates a much higher ruggedness of the SiC devices under electro-chemical stress, as previously reported in [4], this is not necessarily material related, since the considered silicon counterparts are not state-ofthe-art designs anymore, because novel silicon devices feature an improved H 3 TRB performance, too [12]. On the other hand, the Weibull shape factor is much smaller for the SiC devices, which represents the wider failure distribution of the SiC devices. Considering the Weibull scale factors of the three test

PCT after H 3 TRB
The PCT after H 3 TRB was performed on 4 DUTs of test split 3, i.e. the reference split for the H 3 TRB test, which had not been subjected to any preceding stress before the H 3 TRB test. As failure criteria for the power cycling test, a step-increase in V DS was used as an indicator for bond wire failure (BW), and a 15 % increase in Rth was used as failure threshold for chip solder degradation (CSD). The power cycling test was conducted with constant on and off times of 3 s, at a target temperature swing of 100 K, minimum temperature of 30 °C and with a load current of 29.3 A. Due to the effect of a settling process of the thermal interface between DUT and heatsink, common for this package type, the temperature swing dropped by approximately 4 K within the first few 100 cycles. For that reason, the actual temperature swing was slightly lower than targeted.

Failure Mechanism
The characteristics of V DS and Rth of all 4 DUTs are shown in Fig. 6. All DUTs exhibited an increase in V DS and Rth towards their parametric end of life. Three of the four devices showed only a gradual increase of V DS and Rth and surpassed the CSD failure criterion of 15 % increase in Rth without any indication of bond wire failure. One DUT exhibited multiple step increases in V DS, indicating bond wire failure, shortly before the Rth failure criterion was met. Previously published power cycling test results for modules of the same production lot [6] showed that the dominating failure mode for the applied test conditions is CSD, but some bond wire failures can be expected as well. Therefore, the results of this test do not indicate a shift in failure mode due to the preceding H 3 TRB test. Since the Rth only indicates degradation of the thermal path without further information about the location, the thermal impedance characteristics Zth was also monitored frequently during the test. The Zth characteristics of one DUT during the PCT run 3 is shown in Fig. 7. The Zth characteristics exhibit a change in the time domain of 1 ms to 10 ms in the measurement taken at 17 kcycles. Degradation in this time domain is typical for chip solder degradation of this package type [10], which confirms that the underlying failure mechanism of the DUTs was indeed CSD.

Lifetime Analysis
The test results are shown in the lifetime plot in Fig. 8, with the cycles to failure corresponding to the Weibull scale factor and the error bars indicating the standard deviation of ∆ T vj for the x-axis and N f for the y-axis, respectively. As a reference, a lifetime model obtained for identical devices of the same production lot, is also shown [6]. The lifetime model is obtained by a parameter fit on the simplified CIPS08 model according to the inset equation in Fig. 8. The corresponding parameters for the devices under test as well as for comparable silicon devices in the same package are given in the inset table in Fig. 8. As published before [6], the number of cycles to failure of the SiC MOSFETs is only approximately 25 % of the number of cycles to failure of their silicon counterparts, which is consistent with other studies [13,14]. Considering the respective error bars, the data point for the results of the PCT after H 3 TRB is in good agreement with the lifetime model for the module under test. This indicates that the preceding H 3 TRB stress of several thousand hours did not affect the power cycling capability of the modules.

Summary and Conclusion
In this work, a possible interaction between electro-chemical and thermo-mechanical stress was investigated by consecutive H 3 TRB and PCT testing. For that purpose, an H 3 TRB test was performed on devices, which had been previously exposed to power cycling. Vice versa, a power cycling test was performed on devices, which were subject to a preceding H 3 TRB test. As a reference, pristine devices were also tested in H 3 TRB and PCT. The performance of the preconditioned devices during the respective reliability test was not affected by the preceding stress for both test sequences. Therefore, the results of this investigation suggest that there is no significant interaction between thermo-mechanical and electro-chemical stress for the considered SiC power modules and hence, both stressors can indeed be investigated separately. Furthermore, the excellent H 3 TRB performance of the investigated SiC power modules proves, that despite the higher electrical fields of SiC edge terminations, their reliability against electro-chemical stress is not compromised and properly designed SiC power modules are indeed suitable to be operated in harsh environments. reference data for comparable silicon devices for comparison [6]. All 4 DUTs (including the DUT with bond wire failure shortly before the Rth failure criterion was reached) were used for the statistical analysis. The error bars indicate the standard deviation of N f and ∆T vj. The lifetime curves are obtained using a fit on the simplified CIPS08 model according to [6]. The parameter for the impact of T min (β 2 ) was not fitted but taken from the original model.