Small-Signal Impedance and Split C-V Characterization of High-κ SiC Power MOSFETs

In this work, the improvement of SiC power MOSFET performance achieved using high-κ gate-dielectrics instead of the standard SiO2 is investigated by means of advanced gate-impedance characterization. The benefit of using high-κ gate-dielectrics with high dielectric constant is demonstrated by comparing SiC MOSFETs with pure high-κ, a stack of SiO2/high-κ, as well as pure SiO2. Namely, the fabricated high-κ SiC MOSFETs show a superior performance to commercial SiC MOSFETs with SiO2/SiC interface with respect to channel resistance and interface quality. The proposed characterization approach is non-destructive and applicable to packaged power devices.


Introduction
In comparison to Si device technology, threshold voltage instability due to traps at the SiO 2 -SiC interface has turned out to be a characteristic feature of SiC power MOSFETs [1]. It has been recently shown that high-κ gate dielectrics replacing native SiO 2 represent a promising solution for improving the performance of vertical SiC power MOSFETs with respect to threshold voltage hysteresis and threshold voltage shift under gate stress [2]. An improved interface quality furthermore enables achieving lower specific on-state resistance [3]. In this paper split C-V and small-signal impedance characterization of pure high-κ, SiO 2 /high-κ and pure SiO 2 SiC power MOSFETs are compared, in order to analyze the impact of gate-dielectrics on the device performance.

Small-Signal Impedance Characterization
Small-signal impedance measurements are performed to extract datasheet device characteristics such as internal gate resistance and capacitance-voltage behavior. Split C-V characterization on the other hand is typically used to measure the reverse power MOSFET capacitance, C rss . In this paper, the gate impedance is measured to evaluate the internal gate resistance as function of frequency and gate bias, while split C-V measurements at different frequencies are performed to evaluate the gate-drain C dg and gate-source C sg capacitances, separately. Furthermore, the channel R ch and drift resistance R drift (= R jfet + R epi + R sub ) components of the total on-state resistance are extracted based on the split C dg and C sg measurements as described in [4]. All measurements are performed using a Keysight E4990A impedance analyzer for the SiC power MOSFET samples specified in Table 1.

Split C-V gate characterization: Results
From the split C-V measurements, C dg and C sg components can be either extracted using a series (C s -R s ) or parallel (C p ||G p ) equivalent model, where the peaks observed in the series C sg,s and C dg,s can be correlated to the transconductance g m extracted from the transfer-characteristic I d -V gs as described in [4]. The C sg and C dg of K1, S1, M1 and M2 measured at f = 30 kHz are shown in Fig. 1. Comparing C dg,s and C sg,s of K1, S1, M1, and M2 SiC power MOSFETs, higher peaks within C sg,s and C dg,s of K1 point out to higher transconductance for high-κ-than for high-κ/SiO 2 and pure SiO 2 -interface. Furthermore, an improvement of SiC power MOSFET technology from Wolfspeed from Gen2 to Gen3 with respect to g m can be clearly observed by comparing M1 and M2.

Extraction of on-state resistance components: Results
Since the parallel capacitances C sg,p and C dg,p carry only the information about MOSFET capacitances and not about g m , C sg,p and C dg,p are used to evaluate the R ch /R drift ratio as shown in Fig. 2a). The total drain-to-source on-state resistance R ds,ON is evaluated from I d -V gs measurements at V ds = 50 mV, thus allowing the evaluation of individual components R drift and R ch as function of V gs . The R drift and R ch results normalized by device active area are shown in Fig. 2b). First, a dependence of R ch and R drift on the pitch size can be extracted from Fig. 2b) by comparing K1 and K2 SiC power MOSFETs. Second, the proposed characterization method clearly points to reduced R ch and R drift of SiC power MOSFETs K1 and K2 with pure high-κ gate-interface than in the case of S1 and S2 with high-κ/SiO 2stack. Another interesting observation is that R ch of K1 and M2 are comparable despite a smaller pitch of M2 that can be explained by (1) increased C ox , i.e. higher transconductance of the MOSFET g m , and (2) an improved channel mobility due to higher interface quality.
10 11 12 13 14 15 1 Fig. 2: Extracted a) R ch /R drift ratio and b) R drift and R ch components normalized by device active area and shifted by V th of SiC power MOSFET samples K1, K2, S1, S2, M1 and M2.

Internal Gate Resistance R gg Characterization
Internal gate resistance R gg is extracted as the real part of the measured gate impedance Z gg . The measured R gg of K1 at the gate-source voltage V gs = 0 V and 15 V is presented in Fig. 3a). Typically, in datasheets only R gg at f = 1 MHz and V gs = 0 V is provided. However, R gg is V gs -and f -dependent and three regions as highlighted in Fig. 3a) can be distinguished: 1) very high R gg at low frequency decreasing with f , 2) R gg approximately constant in the mid-frequency range below few MHz, and 3) the high-frequency range above 10 MHz with R gg decreasing. Region 1 can be related to dielectric-SiC interface traps; Region 2 to the resistance of the polysilicon gate and metal-gate runner, and Region 3 represents the distributed behavior of the polysilicon gate layout that becomes dominant at fast switching transients [5]. The equivalent model shown in Fig. 3b) can be used to describe this behavior, where C gg represents the input gate-capacitance, R g,int stands for the resistance of the polysilicon gate and G p models the dielectric "leakage". With smaller G p and higher C gg , Region 2 of R gg (f ) is extended in the lower frequency range, while higher G p and smaller C gg shorten Region 2. Since G p can be high for SiC power MOSFETs because of the high defect density at the SiC-dielectric interface, R gg at 1 MHz can often include the effect of traps and hence, R gg,1MHz can be misleading for evaluating the actual internal gate resistance. The measured R gg (f ) at V gs = 0 V of SiC power MOSFET with high-κ and high-κ/SiO 2 -stack K1, K1b, K2, K2b, S1 and S2 are shown in Fig. 4a), while R gg (f ) of commercial SiC power MOSFETs M1, M2, and M2b are presented in Fig. 4b). In the frequency region between ≈ 20 MHz-100 MHz, R gg of K1, K1b and S1 SiC power MOSFETs overlap, c.f. Fig.  4a), which corresponds to Region 2 marked in Fig. 3. Namely, as K1, K1b and S1 are only different with respect to dielectric-semiconductor interface, the measurements confirm that R gg in Region 2 is determined only by the polysilicon and metal resistance of the gate layout. On the other hand, it can be seen that the quality of the dielectric-semiconductor interface affects Region 1 of R gg , i.e. a  higher interface quality leads to a smaller G p in the model shown in Fig.3b), however this effect can not be fully distinguished from the C gg variation between samples due to different dielectrics. K1 with an improved high-κ dielectric in comparison to K1b, obtained with a better deposition approach, has the smaller G p than both K1b and S1, which can be related to reduced dielectric and interface-traps. Similarly, K2 has the smaller G p than K2b and S2 SiC power MOSFETs. Furthermore, it can be seen that pitch size also affects the equivalent lumped R gg in Region 2. The measurements in Fig. 4b) suggest that G p,M2 and G p,M2b are smaller than G p,M1 , i.e. Region 2 is shifted towards lower frequencies, however gate design parameters affecting C gg also have an influence on Region 1.The clear distinction between these two concurring effects impacting Region 1 is under further investigation.

R gg as function of gate-source Voltage V gs
In the next step, R gg was characterized as function of gate-source voltage V gs . R gg,M1 (V gs -V th ) normalized by the device active area (mm 2 ) is shown in Fig. 5a) for f = 30 kHz, 100 kHz, 1 MHz and 10 MHz. Sweeping V gs is expected to reveal the impact of traps at different energy levels in the bandgap on the R gg . At high frequencies, i.e. 10 MHz, the traps are ineffective and the R gg is independent from V gs and only determined by the gate-layout as discussed for Fig. 3a). R gg (V gs -V th ) normalized by the device active area (mm 2 ) of K1, K2, S1, S2, M1, and M2 are presented in Fig. 5b) and Fig. 5c), without and with scaling with the pitch size, respectively. The lower peaks amplitude of the high-κ samples and M2 further support the conclusion of higher interface quality of these samples and/or higher C gg . Interestingly, M1 shows a peak in the positive V gs -V th range suggesting the presence of different interface traps closer to the conduction band, which have been removed in the latest Wolfspeed device generation. The scaling by the pitch size is necessary to make more meaningful comparison of different devices, namely in Fig. 5c) the peak amplitude for the same technology are equalized independently on the cell pitch: K1-K2 and S1-S2. The V th hysteresis of K1, S1, M1 and M2 is shown in Fig. 5d). M2 presents a significant V th hysteresis despite the smaller R gg (V gs ) peak shown in Fig. 5c) and the small C ox of SiO 2 , that can lead to the conclusion that the defects affecting R gg (V gs ) differ from the

70
Technologies and Application of Engineering Materials defects impacting the V th -hysteresis [6]. It should be noted that pure high-κ dielectric shows negligible hysteresis in comparison to SiO 2 /high-κ and pure SiO 2 samples.

Summary
This work reveals the benefit of high-κ gate dielectrics for SiC power MOSFETs and also demonstrates that the standard small-signal impedance measurements can be extended for more precise information on device performance and application-relevant characteristics. The presented gate impedance characterization can be adopted as non-destructive investigation approach to analyze the device quality with special focus on the SiC/gate-dielectric interface for packaged semiconductor devices.