TI-ADC multi-channel mismatch estimation and calibration in ultra-high-speed optical signal acquisition system

: This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implemented in 28 nm CMOS, reaches a 41 dB SFDR with an input signal of 1.2 GHz and 5 dBm after the proposed background offset and gain mismatch calibration. Compared with previous works, the spurious-free dynamic range (SFDR) and the effective number of bits (ENOB) are better, the estimation accuracy is higher, the error is smaller and the faster speed of convergence improves the efficiency of signal processing.


Introduction
With the popularization of Internet, various new media promote the explosive development of the network industry. The transmission bandwidth requirements of metropolitan area networks and backbone networks continue to increase. Reference [1] proposes a method which includes two pilot scheduling schemes, fractional pilot reuse (FPR) and asynchronous fractional pilot scheduling (AFPS) scheme, which significantly mitigate the personal computer (PC) in the uplink time division duplex (TDD) massive multiple-input-multiple-output (MIMO) system. Reference [2] describes a machine learning and deep learning concepts in optical 5G network, they collect the data first, and operate the optimal weighted feature extraction (OWFE), then they finish the slicing classification. Their model can influence the provision of accurate 5G network slicing. In 5G communication and MIMO system, there are still many challenges to the deployment of transmission systems. In order to transfer the photoelectric conversion analog signals into the digital domain, ADC plays an important role.
The traditional intermediate frequency (IF) signal acquisition platform is shown in Figure 1. With the help of a software radio structure, the microwave signal received by the antenna is mixed, converted into an IF signal, and then it is sampled after the signal conditioning links such as amplification and filtering; however, for the 20 Gbps radio frequency signal, the IF method cannot directly sample the radio frequency signal, so the radio frequency (RF) signal sampling structure is created, which is shown in Figure 1. First, it receives the radio frequency signal, and passes through a filter to reduce noise. After filtering through a low noise amplifier (LNA), it enters the ADC to achieve analog-to-digital conversion. Compared with the traditional sampling method, the structure is simpler and it is more suitable for high-bandwidth signals. In order to meet the requirements of RF signal sampling frequency, the sampling method of multichannel time interleaving is proposed and widely used in ultra-wideband communication and highspeed serial communication. The structure and clock phase are shown in Figure 2, M channels sample alternately, and the sampling frequency becomes M times that of a single channel. Although the time interleaved technology increases the sampling frequency on the limited hardware resources, due to process issues and device aging, stress imbalance and temperature drift, etc., the gain, offset and delay of each channel will be randomly distributed (gain and offset are the values by which the input values are multiplied and then to which the input values are added, respectively), and such errors will be amplified several times under the influence of high speed, which seriously affect the accuracy of ADC, so ADC calibration becomes a key step in the process of digital signal. In recent years, scholars have mostly used equalization technology, adaptive blind correction, and random chopping sampling technology for calibrating the channel mismatch. Some works propose inter-channel equalization technology to solve the gain mismatch [3][4][5][6], they divide the convergence process into several phases and assist with a monotonicity detector to decide when to shift from one phase to the next phase. Selecting one of the channels as the reference channel will cause the channel to fail to perform self-calibration, and the calibration model lacks completeness, secondly, the addition of the reference channel makes the input impedance change, which is an obvious shortcoming for ultrahigh-speed ADCs. The method proposed in [7] is to estimate the mismatch between channels, the technique is based on the discrete Fourier transform (DFT) for estimating and correcting gain mismatch and timing error in an M-ADC, which also describes the influence of these mismatches, however, the research does not propose a method to compensate the offset error, the technique is lack of integrity. In [8], an fast Fourier transform (FFT)-based method to evaluate and compensate offset and gain errors in time-interleaved ADC system is proposed with a known sinusoidal input. In [9], a digital background calibration method is proposed to calibrate the offset and gain mismatch as well as the timing error.
Reference [10] proposes a digital hybrid background calibration for time delay, with a 5 GS/s 29 mW TI successive-approximation-register (SAR) ADC, and the calibrated signal noise distortion rate (SNDR) reaches 48.5 dB (which is also called signal-to-noise-and-distortion ratio (SINAD) officially in the IEEE Standard, in order not to confuse the two definitions (SNDR and SINAD) later in the text, the subsequent exposition is consistent with the standard and is referred to as SINAD). They use a model of parameter mixed between channels, and estimate the time delay based on Nyquist frequency, the method is divided into 4 steps to achieve channel alignment. Finally, the calibration is completed in the order of offset and gain. However, the reason for the offset and gain mismatch is attributed to the delay in the article, after estimation and compensation, the offset and gain mismatch are resolved. For ultra-high-speed optical signal acquisition systems, the sources of mismatch are more complicated, and the effects of offset and gain need to be considered separately on the basis of completing channel alignment. Reference [11] divides the TI structure into two topological structures, which improves the convergence speed of time offset calibration, and SINAD can reach 54.2 dB; Reference [12] mainly introduces the calibration of bandwidth mismatch, based on the traditional method, constructs a kind of FIR filter to implement signal compensation. References [9] and [13] describe an algorithm for evaluating ADC performance, and comprehensively analyzes the impact of bandwidth mismatch on sampling. References [14,15] are different from the traditional background calibration, the calibration method of the digital-to-analog converter (DAC) in the feedback link is introduced, which further improves the calibration effect. References [16][17][18] analyze the influence of channel mismatch sampling, they use the channel cross feedback mechanism to equalize the mismatch, and design a peripheral delay circuit to compensate for the offset of the calibration clock, which eliminate the energy of harmonics, and improve SINAD; References [19][20][21][22] propose a background calibration method that does not require pre-emphasis based on a 65 nm, 6-bit, 16 GS/s TI ADC. The offset mismatch is reduced after digital calibration, the delay phase locked loop is used to generate 8 sampling interfaces as multi-phase clock generator; References [23][24][25] propose a blind method to estimate channel mismatch and timing skew, this method does not need to know the input signal, as long as it meets the required bandwidth, calibration can be done while ADC is converting, it can be applied to many environments. The above works are all carried out around the background calibration. Compared with the foreground calibration, the background calibration can better monitor the power and temperature of the system, besides, it will not affect the normal sampling of the ADC. 1241-2010 IEEE Standard in [26] provides the standard for terminology and test methods for analog-to-digital converters, which also includes the method to calculate the gain and offset mismatch.
Different from the previous research works, this article does not select an actual channel as the reference channel, which means all channels can be calibrated and there is no impedance mismatch. When every channel meets the standard (offset and gain error are 0), the calibration is completed, otherwise, calibrate it until convergence. We estimate the mismatch first and design a channel equalization structure to calibrate, such method can reduce the error and the signal quality is further improved. Besides, there are a variety of random noise in the complex transmission channel, traditional methods are not stable especially at a high sampling frequency, however, Monte Carlo method happens to be flexible to deal with these random issues, so the relative error of estimation is smaller and reduces the number of iterations. After calibration, the SFDR reaches 41.72 dB and the SINAD increases from 21.65 dB to 30.16 dB, the signal-to-noise ratio (SNR) improves from 21.91 dB to 30.58 dB and ENOB achieves 5.76 bits, such method shows a better performance than other methods in the same experiment condition.
The rest of this article is organized as follows: Section 2 describes the impact of mismatch on ADC. Section 3 reviews the accumulative average algorithm used in the channel equalization process. Section 4 describes the improvement of the channel equalization algorithm. Section 5 is the hardware implementation and experiment results compared with other art works. Section 6 draws the conclusion.

The influence of mismatch
There are two versions to define the gain and offset: 1) (independently based) gain and offset are the values by which the input values are multiplied and then to which the input values are added, respectively, to minimize the mean squared deviation from the output values. 2) (terminal based) gain and offset are the values by which the input values are multiplied and then to which the input values are added, respectively, to cause the deviations from the output values to be zero at the terminal points, that is, at the first and last codes. In order to verify the derivation, we simulate the mismatch by a 4channel 8-bit ADC with the sampling frequency at 40 GS/s, there are two types of input signals: the input frequency is 1.2 GHz and 12 GHz, both voltage of the input signal is 1 V.

Analysis of offset mismatch
Because the processing is performed in the digital domain, the processing process is based on the binary output, the input of the circuit is a standard sinusoidal signal, therefore, in the complete cycle, the average value of the output code is 0, compared the actual average value with 0 can get the offset mismatch. The same input voltage, output different codes, subtracting a calibrated offset mismatch from this code is the output result after calibration. The conversion structure is shown in Figure 3(a), each channel has an offset mismatch [27], the mismatch cause the transfer curve to deviate from the ideal curve, as shown in Figure 3(b). At the same time, the temperature drift and stress of the chip will also affect it. A certain range of fluctuations are generated on the input analog voltage. Such fluctuations are randomly distributed among the sub-ADCs (SADCs), and there is a positive or negative shift. Each channel has a different offset mismatch , , … , , since each channel works alternately, the offset mismatch can be seen as periodic noise, which can be expressed as: in the time domain, the noise sequence can be expressed as: (2) where is the sampling period, in order to identify the influence of the harmonics caused by the offset mismatch, Fourier transform of Eq (1) can be represented as: bring Eq (3) into the output signal: it can be seen from Eq (4) that the offset mismatch will produce harmonic components at / , 0,1,2, … , 1, is the sampling frequency, since the DFT has symmetry, this article takes the spectrum of one side, and the harmonics of the other half are the same. When the ADC only has an offset mismatch, for example, simulate the offset in the 4-channel ADC, we set the root mean square (RMS) and the range of offset to 0.29 V and 0.5 V respectively, Figure 4(a),(b) show the comparison between ideal and mismatch sampling sequence, the offset mismatch of each channel is different, and they all deviate from the ideal sampling point. As shown in Figure 4(c),(d), the spectrum contained M-1 harmonic components.

Analysis of gain mismatch
The gain mismatch is generally caused by the mismatch of the ADC reference voltage, capacitance or device, the amplitude of the output signal is inconsistent with the ideal case, it is just a ratio without unit. The ADC used in this article integrates 128 SADCs, each 8 SADCs are combined to form 16 channels. Due to the different positions of the SADCs on the chip, uneven temperature and unbalanced forces, each ADC has a randomly distributed gain mismatch. In an ideal case, the gain is 1, but due to the above reasons, the gain of each channel is randomly distributed within a certain range above or below 1. The mismatch model is shown in Figure 5(a), and Figure 5(b) shows a comparison between ideal transfer curve and actual curve with gain mismatch. Each sub-channel ADC has a different gain , , … , . As shown in Figure 5(a), due to the periodic alternating work of each channel ADC, the gain mismatch can be seen as the sequence noise, which can be expressed as: … , , , … , , , , … , , , , … in time domain, Eq (5) is represented as: (6) in order to facilitate analysis, Eq (6) is transformed into frequency domain after Fourier transform: assume there is only a gain mismatch in the time-interleaved ADC system, the output sequence can be expressed as: gain mismatch will cause the nonlinearity of the time-interleaved ADC output, which appears as periodic noise in the time domain, and as high-energy harmonics at a fixed frequency in the frequency domain. The frequency position where the peak of the harmonic spectrum appears for: In the simulation with gain mismatch only, we set the RMS to 1.01, and the range of the gain mismatch is 1.30, the sampling sequence is shown in Figure 6(a),(b). The inconsistency of the gains between the 4 channels causes the sampling point to deviate from the ideal sampling point. The mismatched spectrum is shown in Figure 6(c),(d). Large harmonic components are produced at the frequency / , which have an impact on the signal, different input frequencies lead to different harmonic positions within a limited spectrum.

Analysis of clock jitter
The jitter of the clock causes delay in the sampling time of different channels, the clock diagram with time delay is shown in Figure 7(a), which make the actual sampling point deviate from the ideal sampling point shown in Figure 7  The clock phase generated by the ideal clock is and the jitter is , the sampling points are different from ideal case, the sequence can be expressed as: where is the sampling sequence of channel , is the input signal, and • is the sampling pulse sequence, • can be represented in frequency domain as: As a result, can be represented in frequency domain as: where can be represented as: 1 As we can know from Eq (13), the jitter of sampling clock can cause several harmonic components at / 1,2, 1 in the spectrum, in the simulation, we set the RMS to 14.53 ps, and the clock jitter range is 1/ , as shown in Figure 8  The energy of the effective signal in the output spectrum can be represented as: The noise power caused by clock jitter can be represented as: According to the Parseval theory, As a result, the SNR can be represented as: where ∑ cos Ω Δ , ∑ , Eq (17) shows that noise and input frequency can influence the SNR seriously.

Offset mismatch calibration using equalization algorithm
According to the channel equalization method, we construct the offset mismatch calibration diagram shown in Figure 9. The model ACC&AVG indicates the accumulative average method. The specific process is:  According to the accumulative average method, calculate the initial offset mismatch 0,1, … , 1 according to Eq (18), and obtain by taking the difference between and , , 0  where is the actual sampling sequence, is the number of channels, N is the total number of sampling points, and is the direct current (DC) offset of the signal under ideal case, 0.  According to Eq (20), the offset correction amount , is initialized, the result is stored in the register, and , is updated according to Eq (21). , , , where is the calibration step size, which determines the number of iterations and calibration accuracy of the calibration algorithm.
 Calibrate the output data according to , to get the updated sequence , .
, , , Update the calibrated data to once in step 2 and repeat the above algorithm, until approaches and approaches a fixed value.

Gain mismatch calibration using equalization algorithm
Similar to the calibration of offset mismatch, the gain calibration is shown in Figure 10. The specific derivation process is presented as follows:  According to the accumulative average, the gain mismatch is initialized according to Eq (23), and the difference between and is expressed by :  Initialize the gain correction amount according to Eq (25), and update according to Eq (26): where is the calibration step size, which determines the number of iterations and calibration accuracy of the calibration algorithm.
 Use to calibrate the signal to get the updated sequence , : ,  Update the calibrated data to once in step 2 and repeat the above algorithm. approaches , approaches a fixed value, and the calibration is completed.

Mismatch estimation and calibration based on Monte Carlo method
Monte Carlo method, also known as statistical simulation method, is a general term for ideas or methods, rather than algorithms in the strict sense [28,29]. The advantage of this method is that it can better deal with the randomness problem in the communication system: the mismatch of each channel is stable and unchanging, and the constant characteristics can be used to iterate; but the quantized noise is different in each measurement, and noise varies non-linearly with time, which is in line with the characteristics of probability and statistics. Follow the steps below to build a Monte Carlo model:  Construct or describe the random process: The random noise generated by the mismatch allows the probabilistic process to be established, although each ADC has its own different true value of mismatch, but the result of each estimated mismatch is random.
 Sample from a known probability distribution: Because the estimated mismatch noise is different each time, the output result of is different, but the sequence noise is periodically randomly distributed and has regularity.
 Obtain estimation results. The estimation diagram is shown in Figure 11. The input signal is sampled by ADC to obtain , and is subjected to least square fitting. The gain mismatch , offset mismatch and time delay Δ are included in the parameters , , ; the ideal sequence is interpolated by finite impulse response (FIR), after the mismatch model, the unknown mismatch Δ , , are added and the actual output sequence is equal, and the equation is constructed and solved using the equal relationship between them. The specific solution process is as follows: the ideal input signal can be expressed as: where is the signal amplitude, is the signal frequency, is the phase, and is the DC bias. The actual sampling sequence can be expressed as: where is the quantization parameter, , , is the channel noise, and is the number of sampling points. The actual output of is: There are many ways to estimate parameters. This article uses least square (LS) to complete fitting. By calculating the minimum value of Eq (31), the best estimation result is: (31) where is the actual sampling sequence, cos cos sin , cos , . The actual output after fitting is: For the case of no mismatch between , the output of can actually be understood as the output of obtained through n-fold interpolation [30,31]. Therefore, when performing LS fitting on an ideal channel, an ideal sequence can be obtained through an interpolation filter. This article uses Chebyshev I-type interpolation filtering to simulate two-channel ADC interpolation. First, is twice interpolated, and the upper limit of passband lost is set 0.1, the lower limit of stopband loss is 1, and the normalized band angle frequency 0.4, the stopband corner frequency 0.6 , after calculated through the above parameters, the filter order 2 and the cutoff frequency 0.4, besides, as shown in Figure 12, the interpolated filter is compared to the initial sequence, the filter contains more points and the error would be reduced.  Fit the output data without mismatch according to the result of interpolation, and the fitted sequence of ideal can be represented as: where ̅ cos , sin . In order to construct a set of equations, add mismatches to the ideal sequence according to Figure  13, add the delay Δ between ADCs, the offset mismatch and the gain mismatch one by one [11]. Due to the presence of noise and mismatch in the channel, the actual output sequence can be expressed as: substituting the expression into Eq (34), can be expressed as: Equations (35) and (32) both represent the actual output of , so the relationship between the ideal sine and the fitted actual sequence is: where and ̅ ̅ are all known, matrix can be represented as: Solve the matrix equation and get the expressions of , Δ and :

Offset calibration with Monte Carlo method
Pack the above algorithm into the model named Cali, replace the ACC&AVG module in the algorithm presented in Section 3, the detailed process is shown in Figure 14:  The input signal enters M SADCs through time interleaving sampling, and the sampled sequence enters the Cali.
 , ；  Repeat the above steps until , approach 0, , approach a constant value. The above-mentioned calibration steps are calibrated to .

Figure 14.
Offset mismatch calibration with Monte Carlo method.

Gain calibration with Monte Carlo method
Similar to calibrate the offset mismatch, calibrate the gain mismatch according to the diagram shown in Figure 15:  The analog signal is input to M SADCs for interleaving sampling, and the sampling sequence output by enters the model Cali.  Fit the sequence and estimate the initial value of the gain mismatch. 1 . Repeat the above steps until , approach 0, and , approach a constant value. The abovementioned calibration procedure is calibrated according to from to . Compared with the inter-channel equalization algorithm proposed in Section 3, the reference channel set in this article is not a channel in the actual ADC, but an ideal ADC with offset mismatch 0 and gain mismatch 1. In the calibrated process, all M channels are compensated, and the final sequence is close to the ideal value. The new reference channel does not occupy more logic resources and consume more power consumption; in addition, the initial mismatch will also be compensated in an iterative manner. Therefore, the accuracy requirements of this article are not as strict as those mentioned in [7], and the accuracy of calibration mainly depends on the calibration factor . This method reduces the number of estimates and the amount of calculation. Figure 15. Gain mismatch calibration with Monte Carlo method.

Experiment results
The layout design and power consumption of the ADC are shown in Figure 16(a), and the size is 21 mm 21 mm. The ADC is calibrated using the method in Section 4. The signal supply source is shown in Figure 16(b). The signal generator from Rohde Schwarz is used to input a 1.2 GHz and 5 dBm sinusoidal signal and enter the experimental platform through the RF interface. The actual platform is shown in Figure 16(c): The daughter card in the lower right corner is equipped with a 16channel 8-bit ADC with a sampling frequency of 40 GS/s, and the reference voltage is 1.2 V, which is connected to the motherboard through the FPGA mezzanine card (FMC) interface, and the FMC connector establishes a connection with the FPGA through the gigabit transmitter in Y-version (GTY) high-speed port. The test environment and related indicators are shown in Tables 1 and 2

Offset calibration
On the premise that the channel is aligned, the offset mismatch is calibrated. The spectrum before and after calibration is shown in Figure 17. The harmonic components are suppressed and the SFDR is improved. The other parameters are shown in Table 3.
(a) (b) Figure 17. Spectrum before and after offset calibration. The experimental results show that the offset calibration algorithm is effective. The mismatch between channels is compensated.
After 100 iterations of the algorithm, the relationship between related parameters and the number of iterations is shown in Figure 18. Within the first 20 calibration iterations, the rate of change of the parameters is larger and the convergence speed is faster. After 50 iterations, it is basically stable. The offset mismatch of each SADC approaches , and the difference between the two approaches 0. The calibration value approaches a constant value, and the value is written into the M registers of the FPGA. The subsequent sampling sequence directly uses the register value, the result is compensated without iteration.

Gain calibration
Compensate the sampling sequence according to the calibration algorithm of gain mismatch, and the spectrum is shown in Figure 19. The comparison before and after shows that the harmonic components are reduced after the algorithm. The test parameters are shown in Table 4. The experimental results show the algorithm in Section 4 is also effective in compensating for gain mismatch.
(a) (b) Figure 19. Spectrum before and after gain calibration. Gain is the ratio of the output signal to the input signal without unit, so there is no unit of the relevant parameters. Similar to the offset calibration, after 100 iterations of the algorithm, the relationship between the relevant parameters and the number of iterations is shown in Figure 20, the calibration parameters within 20 times have a large change rate and a fast convergence speed. All parameters converge around 50 iterations, for each SADC, its gain mismatch approaches , and the difference approaches 0. The calibration amount approaches a constant value, and this value is written into the M registers of the FPGA. The subsequent sampling sequence directly uses to compensate the signal without calibration. The relationship curve between ( and ) and the number of iterations is shown in Figure 21. Although is less than 1, the number of iterations decreases with the increase of , which reduces the amount of calculation, but it affects the accuracy of calibration. When it is greater than 1, the number of iterations will increase accordingly. Therefore, setting appropriately can balance the calculation complexity and the calculation accuracy.

Comparison between this work and previous works
In order to verify the advantages proposed in this article, a series of comparative experiments are completed under the same conditions, the details are as follows.
The initial mismatch must be estimated before the calibration, the initial estimation accuracy affects the subsequent operations, we evaluate relative error after the first estimation, it is an average relative error of all SADCs, its unit is %, which can be represented as:

100%
(39) where is the relative error, is the estimated mismatch, and is the conventional true value of the mismatch after enough experiments. We compare the relative error with the accumulative average method and method proposed in 1241-2010 IEEE standard [26], in the standard, gain and offset are represented as: where is the ideal width of a code bin, that is, the full-scale range divided by the total number of codes, is the resolution of ADC, is the input value corresponding to the transition between codes and 1. Table 5 shows the comparisons of relative errors, references [3] and [4] represent the accumulative and average method, the Monte Carlo method in this article shows smaller relative error and higher estimation accuracy than others. After estimating the initial mismatch, we also use the method presented in [3] and [4] to calibrate the ADC in the same experiment condition, the testing parameters are compared in Table 6, the proposed method has better calibration performance, higher accuracy and faster convergence than [3] and [4], the signal quality improves more and the harmonic components caused by the channel mismatch are suppressed. where is the measured quantity, ̅ is the average of , is the number of measurements, the of SINAD, SNR, SFDR and ENOB are listed in Table 7, which shows the possibility to compare this work with [3] and [4]. Some art works only present the method to calibrate gain mismatch, so we compare the gain error with other art works, different from the relative error, the gain error is calculated after calibration and it is an absolute error, which can be represented as: where is the gain of after calibration, is the number of channels, this error represents the degree to which the calibrated signal is close to the ideal signal, which is also one of the indicators for judging the performance of calibration. As shown in Table 8, the gain error is smaller than previous works, shows better signal quality after calibration.

Conclusions
This article proposes a method that uses Monte Carlo to estimate the mismatch between ADC channels and combines the channel equalization method to calibrate the offset and gain mismatch. Such method does not need an actual channel as the reference, it is a global calibration, and there are no additional circuits. Compared with the accumulative average method, Monte Carlo method is more stable in the face of random noise. It can flexibly grasp the dynamic changes of transmitted data and does not require additional front-end processing circuits; besides, the estimation is more accurate compared to just average the mismatch, and high-precision estimation shortens convergence time. At a sampling frequency of 40 GS/s, a 16-channel TI ADC reaches an SFDR of 41 dB and an SNR of 30 dB, increases the ENOB from 4.06 bits to 5.68 bits, the performance is better than previous works (including IEEE Standard) at the same experiment condition. The results verify the novelty of the method, and highlight the advantages compared to other works in the literature, based on the high accuracy of estimation, this work increases the convergence speed, and saves more power consumption for the subsequent operations, such as frame synchronization, modulation format recognition and carrier recovery. As a result, it is an effective method in ADC calibration.