Formation of high-quality SiC(0001)/SiO2 structures by excluding oxidation process with H2 etching before SiO2 deposition and high-temperature N2 annealing

We formed SiC/SiO2 structures by various procedures that excluded an oxidation process. We found that a SiC/SiO2 interface with a low interface state density near the conduction band edge of SiC (D it ∼ 4 × 1010 cm−2 eV−1 at E c −0.2 eV) is obtained for a fabrication process consisting of H2 etching of the SiC surface, SiO2 deposition, and high-temperature N2 annealing. D it is rather high without H2 etching, indicating that etching before SiO2 deposition plays a significant role in reducing D it. The key to obtaining low D it may be the removal of oxidation-induced defects near the SiC surface.

S ilicon carbide (SiC) metal-oxide-semiconductor fieldeffect transistors (MOSFETs) have attracted considerable attention as promising devices for high-voltage and fast-switching power applications. 1,2) The performance of SiC MOSFETs is constantly being improved. [3][4][5][6][7][8] However, the on-resistance of medium voltage class (∼1 kV) SiC MOSFETs is still dominated by a high channel resistance due to the high density of interface states (∼10 13 cm −2 eV −1 ) in SiC/SiO 2 systems. [9][10][11][12] To reduce the channel resistance, most commercial SiC MOSFETs have relatively short channels (<1 μm). However, further shortening of the channel length is problematic because it will induce short-channel effects, such as decreasing the threshold voltage, non-saturation of the drain current, and subthreshold slope degradation. 13,14) Therefore, it is important to reduce the interface state density (D it ) to improve the performance of SiC MOSFETs.
Post-oxidation annealing of nitric oxide (NO) is commonly used as a passivation method for interface states in SiC/SiO 2 structures. [15][16][17][18][19] NO annealing can improve the channel mobility from 3-5 to 30-40 cm 2 V −1 s −1 . However, further improvements are necessary to take full advantage of the potential of SiC. Various studies have been conducted to achieve high channel mobility. [20][21][22][23][24][25] Several passivation methods have achieved high channel mobility (∼70-100 cm 2 V −1 s −1 ) (e.g. sodium enhanced oxidation 26,27) and annealing in phosphoryl chloride (POCl 3 ) ambient 28,29) ). However, these methods are not suited for industrial applications because of the threshold voltage instability caused by ion drift 30) or carrier trapping. 31) The origin of high D it is unclear at present, though carbon defects are a possible explanation. 9,[32][33][34] Recently, firstprinciples calculations have suggested that dicarbon antisites are very stable under oxygen-rich conditions, and can create defect levels near the conduction band edge. 34) Another possible candidate is conduction band fluctuation. [35][36][37] Research has indicated that high D it may arise from crystalline disorder of SiC surfaces caused by SiC oxidation. Thus, one solution may be elimination of oxidation from the SiO 2 formation process as much as possible. Recently, we reported that a significantly lower D it can be obtained by creating a SiC/SiO 2 structure via Si deposition. 38) In this process, a gate oxide was created by the following process. First, a thin Si film was deposited on a SiC surface after H 2 etching. Then, SiO 2 was formed by oxidation of Si at a low temperature (750°C). Finally, high-temperature N 2 annealing was conducted. The key to obtaining low D it in this process was suppressing SiC oxidation.
In this study, we propose another approach to exclude oxidation process for SiO 2 formation using chemical vapor deposition (CVD). In addition to suppressing SiC oxidation, we have found that surface etching of SiC by H 2 plays a vital role in reducing D it near the conduction band edge (E c ) of SiC. We discuss the possible mechanism of the observed reduction in D it based on our results. We believe the key to obtaining low D it is removing oxidation-induced defects near the SiC surface.
MOS capacitors were formed on n-type 4H-SiC (0001) epilayers (donor density: 1 × 10 16 cm −3 ). The processing conditions for gate oxide formation are indicated in Fig. 1. After RCA cleaning, some of the samples were etched in H 2 ambient at 1350°C and 0.1 MPa for 15 min, giving an etched thickness of about 5 nm. After H 2 etching, sacrificial oxidation was performed at 1300°C for some samples (the oxide thickness was about 18 nm and was removed by buffered HF). Some samples were etched in H 2 ambient again. The gate oxides were deposited by plasma-enhanced CVD at 400°C, resulting in an oxide thickness of 20-30 nm. Then, hightemperature N 2 annealing 39,40) at 1400°C for 45 min or Ar annealing at 1400°C for 10 min was performed. Finally, circular Al electrodes were deposited (diameter: 300-500 μm). Designations for the prepared samples are indicated in Fig. 1. For comparison, MOS capacitors with SiO 2 (thickness: 30 nm) formed by dry oxidation were prepared. NO annealing was performed at 1250°C for 70 min. The sample not subject to annealing is designated "As-Ox." Figure 2(a) depicts the quasi-static and 1 MHz capacitance-voltage (C-V ) characteristics of the MOS capacitors at 300 K. High-frequency and quasistatic C-V characteristics were simultaneously measured using KEITHLEY 82 C−V System. Voltage sweeping was conducted from the depletion side to the accumulation side. In the figure, the ideal C-V curve with an oxide thickness of 25 nm and a donor density of 1 × 10 16 cm −3 is also indicated for comparison. A large frequency dispersion is observed for the As-Ox sample. The dispersion is well reduced in the CVD-N 2 sample and further suppression is achieved by performing H 2 etching prior to SiO 2 deposition (H 2 -CVD-N 2 sample). The densities of the effective fixed charge estimated from the flat-band voltage shifts are 6.7 × 10 11 cm −2 (negative), 7.5 × 10 11 cm −2 (positive), and 1.7 × 10 12 cm −2 (positive) for the As-Ox. sample, the CVD-N 2 sample, and the H 2 -CVD-N 2 sample, respectively. Figure 2(b) illustrates the energy distributions of D it estimated by a high (1 MHz)-low method. Note that the hysteresis of the C-V characteristics was negligibly small and the energy distribution of D it was almost uniquely determined regardless of the sweeping direction. Compared with the As-Ox sample, a ten-fold reduction in D it is achieved in the N 2 -annealed samples with the SiO 2 formed by either SiC oxidation or SiO 2 deposition. The D it for the Ox-N 2 sample is comparable to that of the CVD-N 2 sample. As expected from the C-V characteristics [ Fig. 2(a)], a marked reduction in D it    is about one order-of-magnitude lower than the reported D it for an N 2 -annealed sample with a pre-annealing process (4 × 10 11 cm −2 eV −1 at E c -0.2 eV) 41) and for the NO sample. These results indicate that removal of surface defects is essential for a substantial reduction in D it .
To clarify that SiC oxidation increases D it , we performed sacrificial oxidation after the H 2 etching. Figure 3(a) shows the effect of sacrificial oxidation on D it . The figure shows that D it is not effectively reduced when sacrificial oxidation was performed after H 2 etching (and prior to SiO 2 deposition: H 2 -Ox-CVD-N 2 ), though D it energy distribution is reduced when H 2 etching was performed again after sacrificial oxidation (H 2 -Ox-H 2 -CVD-N 2 ). We also confirmed that the D it energy distribution was not reduced when SiO 2 was formed by oxidation after H 2 etching (H 2 -Ox-N 2 ). The following summarizes the above experimental results: (1) A substantial reduction of D it is achieved by H 2 etching prior to SiO 2 CVD. (2) SiC oxidation results in higher D it even after performing H 2 etching. (3) Even after SiC oxidation, D it decreases when H 2 gas etching is performed again. Based on the above results, we consider that oxidation creates a high density of defects on the SiC surface and these surface defects are the major origin of a high D it at the SiC/SiO 2 interface. The removal of such surface defects might decrease D it , and these defects can be removed by H 2 etching of SiC by about several (∼5) nm. These defects are difficult to directly characterize by standard surface analyses, such as by X-ray photoelectron spectroscopy measurements, because the defects might be formed within only a few sub nm from the SiC surface.
Next, high-temperature Ar annealing was performed instead of N 2 annealing to investigate whether N 2 annealing is necessary for reducing the interface states. Figure 3(b) depicts a comparison of the energy distribution of D it for N 2 -annealed and Ar-annealed MOS capacitors. For Ar annealing, D it is relatively high (1 × 10 12 cm −2 eV −1 at E c −0.2 eV). We also performed forming gas annealing (H 2 /N 2 : 1/9) at 800°C for 2 min after Ar annealing. However, this resulted in only a slightly lower D it than when only Ar annealing was performed.
To evaluate the nitrogen atom profiles near the interface, secondary ion mass spectrometry measurements were performed after depositing SiO 2 and annealing in N 2 at high temperature. Figure 4(a) shows the depth profiles for the nitrogen atom density in samples with and without H 2 etching (CVD-N 2 and H 2 -CVD-N 2 ). The depth profiles for N atoms are almost identical in CVD-N 2 and H 2 -CVD-N 2 , as expected. Figure 4(b) shows the results for NO and N 2 samples for comparison. Inside the oxide material, the nitrogen atom density is about 2-3 times higher in the samples with a deposited oxide than in the samples with a thermal oxide. However, at the interface, the incorporated nitrogen atom density is comparable among all the samples (7-10 × 10 20 cm −3 ). These results suggest that the depth profile for N atoms is independent of H 2 gas etching. Hence, removing C-related defects or a layer with disordered crystallinity near the SiC surface induced by the thermal oxidation of SiC may lower D it . Here, we briefly summarize the key points in common between this study and our previous work 38) for obtaining low D it . There are three common processes: (1) H 2 etching of the SiC surface, (2) SiO 2 formation without oxidation, and (3) high-temperature N 2 annealing. We conclude that all of these processes are necessary for a substantial decrease in D it . Figure 5(a) shows bi-directional 1 MHz C-V curves measured for the H 2 -CVD-N 2 sample (EOT ∼ 20 nm) at 448 K. Before voltage sweeping, a bias voltage of 10 (5 MV cm −1 ) or −10 V was applied for 600 s. Voltage sweeping was immediately conducted in the reverse direction from the initial voltage after the bias stress. The bi-directional C-V curves show a negligibly small hysteresis, meaning that the density of mobile ions and electron traps inside the oxide is negligibly small. Note that the density of holes at the MOS interface without light illumination is extremely low due to the wide bandgap of SiC. Hence, only the electron trapping is evaluated in this measurement. Figure 5(b) depicts the current-voltage (I-V ) characteristics of the prepared SiC MOS capacitors under a positivebias condition (accumulation state). For comparison, the I-V characteristics of the As-Ox, Ox-NO, and Ox-N 2 samples are also indicated. Above 6-7 MV cm −1 , a Fowler-Nordheim (F-N) tunneling current is observed. The breakdown electric fields of the oxides were about 11.5 MV cm −1 for the As-Ox and Ox-NO samples, 10 MV cm −1 for the Ox-N 2 sample, and 10.5 MV cm −1 for the H 2 -CVD-N 2 sample. The breakdown electric field for the H 2 -CVD-N 2 samples is similar to those of other samples.
In conclusion, we demonstrated that H 2 etching prior to SiO 2 deposition is effective in reducing D it at the SiC/SiO 2 (a) (b) interface while suppressing SiC oxidation. A significant reduction of D it (4 × 10 10 cm −2 eV −1 at E c −0.2 eV) was achieved for the procedure of H 2 etching of the SiC surface, SiO 2 deposition, and high-temperature N 2 annealing. C defects induced by the thermal oxidation of SiC are strong candidates for interface states in SiC/SiO 2 systems, and such defects are removed by H 2 etching. Surface etching of SiC before SiO 2 deposition is likely to be the key for obtaining a high quality SiC/SiO 2 structure.